1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 * Copyright 2019 Joyent, Inc.
31 */
32
33 #ifndef _IXGBE_SW_H
34 #define _IXGBE_SW_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include <sys/types.h>
41 #include <sys/conf.h>
42 #include <sys/debug.h>
43 #include <sys/stropts.h>
44 #include <sys/stream.h>
45 #include <sys/strsun.h>
46 #include <sys/strlog.h>
47 #include <sys/kmem.h>
48 #include <sys/stat.h>
49 #include <sys/kstat.h>
50 #include <sys/modctl.h>
51 #include <sys/errno.h>
52 #include <sys/dlpi.h>
53 #include <sys/mac_provider.h>
54 #include <sys/mac_ether.h>
55 #include <sys/vlan.h>
56 #include <sys/ddi.h>
57 #include <sys/sunddi.h>
58 #include <sys/pci.h>
59 #include <sys/pcie.h>
60 #include <sys/sdt.h>
61 #include <sys/ethernet.h>
62 #include <sys/pattr.h>
63 #include <sys/strsubr.h>
64 #include <sys/netlb.h>
65 #include <sys/random.h>
66 #include <inet/common.h>
67 #include <inet/tcp.h>
68 #include <inet/ip.h>
69 #include <inet/mi.h>
70 #include <inet/nd.h>
71 #include <sys/bitmap.h>
72 #include <sys/ddifm.h>
73 #include <sys/fm/protocol.h>
74 #include <sys/fm/util.h>
75 #include <sys/disp.h>
76 #include <sys/fm/io/ddi.h>
77 #include "ixgbe_api.h"
78
79 #define MODULE_NAME "ixgbe" /* module name */
80
81 #define IXGBE_FAILURE DDI_FAILURE
82
83 #define IXGBE_UNKNOWN 0x00
84 #define IXGBE_INITIALIZED 0x01
85 #define IXGBE_STARTED 0x02
86 #define IXGBE_SUSPENDED 0x04
87 #define IXGBE_STALL 0x08
88 #define IXGBE_OVERTEMP 0x20
89 #define IXGBE_INTR_ADJUST 0x40
90 #define IXGBE_ERROR 0x80
91
92 #define MAX_NUM_UNICAST_ADDRESSES 0x80
93 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
94 #define MAX_NUM_VLAN_FILTERS 0x40
95
96 #define IXGBE_INTR_NONE 0
97 #define IXGBE_INTR_MSIX 1
98 #define IXGBE_INTR_MSI 2
99 #define IXGBE_INTR_LEGACY 3
100
101 #define IXGBE_POLL_NULL -1
102
103 #define MAX_COOKIE 18
104 #define MIN_NUM_TX_DESC 2
105
106 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
107
108 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
109
110 #define IXGBE_RX_STOPPED 0x1
111
112 #define IXGBE_PKG_BUF_16k 16384
113
114 /*
115 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
116 * supported silicon types.
117 */
118 #define MAX_TX_QUEUE_NUM 128
119 #define MAX_RX_QUEUE_NUM 128
120 #define MAX_INTR_VECTOR 64
121
122 /*
123 * Maximum values for user configurable parameters
124 */
125 #define MAX_TX_RING_SIZE 4096
126 #define MAX_RX_RING_SIZE 4096
127
128 #define MAX_RX_LIMIT_PER_INTR 4096
129
130 #define MAX_RX_COPY_THRESHOLD 9216
131 #define MAX_TX_COPY_THRESHOLD 9216
132 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
133 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
134 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
135
136 /*
137 * Minimum values for user configurable parameters
138 */
139 #define MIN_TX_RING_SIZE 64
140 #define MIN_RX_RING_SIZE 64
141
142 #define MIN_MTU ETHERMIN
143 #define MIN_RX_LIMIT_PER_INTR 16
144 #define MIN_TX_COPY_THRESHOLD 0
145 #define MIN_RX_COPY_THRESHOLD 0
146 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
147 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
148 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
149
150 /*
151 * Default values for user configurable parameters
152 */
153 #define DEFAULT_TX_RING_SIZE 1024
154 #define DEFAULT_RX_RING_SIZE 1024
155
156 #define DEFAULT_MTU ETHERMTU
157 #define DEFAULT_RX_LIMIT_PER_INTR 256
158 #define DEFAULT_RX_COPY_THRESHOLD 128
159 #define DEFAULT_TX_COPY_THRESHOLD 512
160 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
161 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
162 #define DEFAULT_TX_RESCHED_THRESHOLD 128
163 #define DEFAULT_FCRTH 0x20000
164 #define DEFAULT_FCRTL 0x10000
165 #define DEFAULT_FCPAUSE 0xFFFF
166
167 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
168 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
169 #define DEFAULT_LSO_ENABLE B_TRUE
170 #define DEFAULT_LRO_ENABLE B_FALSE
171 #define DEFAULT_MR_ENABLE B_TRUE
172 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
173 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
174 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
175
176 #define IXGBE_LSO_MAXLEN 65535
177
178 #define TX_DRAIN_TIME 200
179 #define RX_DRAIN_TIME 200
180
181 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
182 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
183
184 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
185
186 /*
187 * Extra register bit masks for 82598
188 */
189 #define IXGBE_PCS1GANA_FDC 0x20
190 #define IXGBE_PCS1GANLP_LPFD 0x20
191 #define IXGBE_PCS1GANLP_LPHD 0x40
192
193 /*
194 * Defined for IP header alignment.
195 */
196 #define IPHDR_ALIGN_ROOM 2
197
198 /*
199 * Bit flags for attach_progress
200 */
201 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
202 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
203 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
204 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
205 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
206 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
207 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
208 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
209 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
210 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
211 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
212 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
213 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
214 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
215 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
216 #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
217
218 #define PROP_DEFAULT_MTU "default_mtu"
219 #define PROP_FLOW_CONTROL "flow_control"
220 #define PROP_TX_QUEUE_NUM "tx_queue_number"
221 #define PROP_TX_RING_SIZE "tx_ring_size"
222 #define PROP_RX_QUEUE_NUM "rx_queue_number"
223 #define PROP_RX_RING_SIZE "rx_ring_size"
224 #define PROP_RX_GROUP_NUM "rx_group_number"
225
226 #define PROP_INTR_FORCE "intr_force"
227 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
228 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
229 #define PROP_LSO_ENABLE "lso_enable"
230 #define PROP_LRO_ENABLE "lro_enable"
231 #define PROP_MR_ENABLE "mr_enable"
232 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
233 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
234 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
235 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
236 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
237 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
238 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
239 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
240 #define PROP_INTR_THROTTLING "intr_throttling"
241 #define PROP_FM_CAPABLE "fm_capable"
242 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
243
244 #define IXGBE_LB_NONE 0
245 #define IXGBE_LB_EXTERNAL 1
246 #define IXGBE_LB_INTERNAL_MAC 2
247 #define IXGBE_LB_INTERNAL_PHY 3
248 #define IXGBE_LB_INTERNAL_SERDES 4
249
250 /*
251 * capability/feature flags
252 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
253 * Separately, the flag named _ENABLED is set when the feature is enabled.
254 */
255 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
256 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
257 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
258 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
259 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
260 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
261 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
262 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
263 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
264 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
265 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
266 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
267
268 /*
269 * Classification mode
270 */
271 #define IXGBE_CLASSIFY_NONE 0
272 #define IXGBE_CLASSIFY_RSS 1
273 #define IXGBE_CLASSIFY_VMDQ 2
274 #define IXGBE_CLASSIFY_VMDQ_RSS 3
275
276 /* adapter-specific info for each supported device type */
277 typedef struct adapter_info {
278 uint32_t max_rx_que_num; /* maximum number of rx queues */
279 uint32_t min_rx_que_num; /* minimum number of rx queues */
280 uint32_t def_rx_que_num; /* default number of rx queues */
281 uint32_t max_rx_grp_num; /* maximum number of rx groups */
282 uint32_t min_rx_grp_num; /* minimum number of rx groups */
283 uint32_t def_rx_grp_num; /* default number of rx groups */
284 uint32_t max_tx_que_num; /* maximum number of tx queues */
285 uint32_t min_tx_que_num; /* minimum number of tx queues */
286 uint32_t def_tx_que_num; /* default number of tx queues */
287 uint32_t max_mtu; /* maximum MTU size */
288 /*
289 * Interrupt throttling is in unit of 256 nsec
290 */
291 uint32_t max_intr_throttle; /* maximum interrupt throttle */
292 uint32_t min_intr_throttle; /* minimum interrupt throttle */
293 uint32_t def_intr_throttle; /* default interrupt throttle */
294
295 uint32_t max_msix_vect; /* maximum total msix vectors */
296 uint32_t max_ring_vect; /* maximum number of ring vectors */
297 uint32_t max_other_vect; /* maximum number of other vectors */
298 uint32_t other_intr; /* "other" interrupt types handled */
299 uint32_t other_gpie; /* "other" interrupt types enabling */
300 uint32_t flags; /* capability flags */
301 } adapter_info_t;
302
303 /* bits representing all interrupt types other than tx & rx */
304 #define IXGBE_OTHER_INTR 0x3ff00000
305 #define IXGBE_82599_OTHER_INTR 0x86100000
306
307 enum ioc_reply {
308 IOC_INVAL = -1, /* bad, NAK with EINVAL */
309 IOC_DONE, /* OK, reply sent */
310 IOC_ACK, /* OK, just send ACK */
311 IOC_REPLY /* OK, just send reply */
312 };
313
314 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
315 0, 0, (flag)))
316
317 /*
318 * Defined for ring index operations
319 * ASSERT(index < limit)
320 * ASSERT(step < limit)
321 * ASSERT(index1 < limit)
322 * ASSERT(index2 < limit)
323 */
324 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
325 (index) + (step) : (index) + (step) - (limit))
326 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
327 (index) - (step) : (index) + (limit) - (step))
328 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
329 (index2) - (index1) : (index2) + (limit) - (index1))
330
331 #define LINK_LIST_INIT(_LH) \
332 (_LH)->head = (_LH)->tail = NULL
333
334 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
335
336 #define LIST_POP_HEAD(_LH) \
337 (single_link_t *)(_LH)->head; \
338 { \
339 if ((_LH)->head != NULL) { \
340 (_LH)->head = (_LH)->head->link; \
341 if ((_LH)->head == NULL) \
342 (_LH)->tail = NULL; \
343 } \
344 }
345
346 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
347
348 #define LIST_PUSH_TAIL(_LH, _E) \
349 if ((_LH)->tail != NULL) { \
350 (_LH)->tail->link = (single_link_t *)(_E); \
351 (_LH)->tail = (single_link_t *)(_E); \
352 } else { \
353 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
354 } \
355 (_E)->link = NULL;
356
357 #define LIST_GET_NEXT(_LH, _E) \
358 (((_LH)->tail == (single_link_t *)(_E)) ? \
359 NULL : ((single_link_t *)(_E))->link)
360
361
362 typedef struct single_link {
363 struct single_link *link;
364 } single_link_t;
365
366 typedef struct link_list {
367 single_link_t *head;
368 single_link_t *tail;
369 } link_list_t;
370
371 /*
372 * Property lookups
373 */
374 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
375 DDI_PROP_DONTPASS, (n))
376 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
377 DDI_PROP_DONTPASS, (n), -1)
378
379
380 typedef union ixgbe_ether_addr {
381 struct {
382 uint32_t high;
383 uint32_t low;
384 } reg;
385 struct {
386 uint8_t set;
387 uint8_t group_index;
388 uint8_t addr[ETHERADDRL];
389 } mac;
390 } ixgbe_ether_addr_t;
391
392 /*
393 * The list of VLANs an Rx group will accept.
394 */
395 typedef struct ixgbe_vlan {
396 list_node_t ixvl_link;
397 uint16_t ixvl_vid; /* The VLAN ID */
398 uint_t ixvl_refs; /* Number of users of this VLAN */
399 } ixgbe_vlan_t;
400
401 typedef enum {
402 USE_NONE,
403 USE_COPY,
404 USE_DMA
405 } tx_type_t;
406
407 typedef struct ixgbe_tx_context {
408 uint32_t hcksum_flags;
409 uint32_t ip_hdr_len;
410 uint32_t mac_hdr_len;
411 uint32_t l4_proto;
412 uint32_t mss;
413 uint32_t l4_hdr_len;
414 boolean_t lso_flag;
415 } ixgbe_tx_context_t;
416
417 /*
418 * Hold address/length of each DMA segment
419 */
420 typedef struct sw_desc {
421 uint64_t address;
422 size_t length;
423 } sw_desc_t;
424
425 /*
426 * Handles and addresses of DMA buffer
427 */
428 typedef struct dma_buffer {
429 caddr_t address; /* Virtual address */
430 uint64_t dma_address; /* DMA (Hardware) address */
431 ddi_acc_handle_t acc_handle; /* Data access handle */
432 ddi_dma_handle_t dma_handle; /* DMA handle */
433 size_t size; /* Buffer size */
434 size_t len; /* Data length in the buffer */
435 } dma_buffer_t;
436
437 /*
438 * Tx Control Block
439 */
440 typedef struct tx_control_block {
441 single_link_t link;
442 uint32_t last_index; /* last descriptor of the pkt */
443 uint32_t frag_num;
444 uint32_t desc_num;
445 mblk_t *mp;
446 tx_type_t tx_type;
447 ddi_dma_handle_t tx_dma_handle;
448 dma_buffer_t tx_buf;
449 sw_desc_t desc[MAX_COOKIE];
450 } tx_control_block_t;
451
452 /*
453 * RX Control Block
454 */
455 typedef struct rx_control_block {
456 mblk_t *mp;
457 uint32_t ref_cnt;
458 dma_buffer_t rx_buf;
459 frtn_t free_rtn;
460 struct ixgbe_rx_data *rx_data;
461 int lro_next; /* Index of next rcb */
462 int lro_prev; /* Index of previous rcb */
463 boolean_t lro_pkt; /* Flag for LRO rcb */
464 } rx_control_block_t;
465
466 /*
467 * Software Data Structure for Tx Ring
468 */
469 typedef struct ixgbe_tx_ring {
470 uint32_t index; /* Ring index */
471 uint32_t intr_vector; /* Interrupt vector index */
472 uint32_t vect_bit; /* vector's bit in register */
473
474 /*
475 * Mutexes
476 */
477 kmutex_t tx_lock;
478 kmutex_t recycle_lock;
479 kmutex_t tcb_head_lock;
480 kmutex_t tcb_tail_lock;
481
482 /*
483 * Tx descriptor ring definitions
484 */
485 dma_buffer_t tbd_area;
486 union ixgbe_adv_tx_desc *tbd_ring;
487 uint32_t tbd_head; /* Index of next tbd to recycle */
488 uint32_t tbd_tail; /* Index of next tbd to transmit */
489 uint32_t tbd_free; /* Number of free tbd */
490
491 /*
492 * Tx control block list definitions
493 */
494 tx_control_block_t *tcb_area;
495 tx_control_block_t **work_list;
496 tx_control_block_t **free_list;
497 uint32_t tcb_head; /* Head index of free list */
498 uint32_t tcb_tail; /* Tail index of free list */
499 uint32_t tcb_free; /* Number of free tcb in free list */
500
501 uint32_t *tbd_head_wb; /* Head write-back */
502 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *);
503
504 /*
505 * s/w context structure for TCP/UDP checksum offload
506 * and LSO.
507 */
508 ixgbe_tx_context_t tx_context;
509
510 /*
511 * Tx ring settings and status
512 */
513 uint32_t ring_size; /* Tx descriptor ring size */
514 uint32_t free_list_size; /* Tx free list size */
515
516 boolean_t reschedule;
517 uint32_t recycle_fail;
518 uint32_t stall_watchdog;
519
520 uint32_t stat_overload;
521 uint32_t stat_fail_no_tbd;
522 uint32_t stat_fail_no_tcb;
523 uint32_t stat_fail_dma_bind;
524 uint32_t stat_reschedule;
525 uint32_t stat_break_tbd_limit;
526 uint32_t stat_lso_header_fail;
527
528 uint64_t stat_obytes;
529 uint64_t stat_opackets;
530
531 mac_ring_handle_t ring_handle;
532
533 /*
534 * Pointer to the ixgbe struct
535 */
536 struct ixgbe *ixgbe;
537 } ixgbe_tx_ring_t;
538
539 /*
540 * Software Receive Ring
541 */
542 typedef struct ixgbe_rx_data {
543 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
544
545 /*
546 * Rx descriptor ring definitions
547 */
548 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
549 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */
550 uint32_t rbd_next; /* Index of next rx desc */
551
552 /*
553 * Rx control block list definitions
554 */
555 rx_control_block_t *rcb_area;
556 rx_control_block_t **work_list; /* Work list of rcbs */
557 rx_control_block_t **free_list; /* Free list of rcbs */
558 uint32_t rcb_head; /* Index of next free rcb */
559 uint32_t rcb_tail; /* Index to put recycled rcb */
560 uint32_t rcb_free; /* Number of free rcbs */
561
562 /*
563 * Rx sw ring settings and status
564 */
565 uint32_t ring_size; /* Rx descriptor ring size */
566 uint32_t free_list_size; /* Rx free list size */
567
568 uint32_t rcb_pending;
569 uint32_t flag;
570
571 uint32_t lro_num; /* Number of rcbs of one LRO */
572 uint32_t lro_first; /* Index of first LRO rcb */
573
574 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */
575 } ixgbe_rx_data_t;
576
577 /*
578 * Software Data Structure for Rx Ring
579 */
580 typedef struct ixgbe_rx_ring {
581 uint32_t index; /* Ring index */
582 uint32_t group_index; /* Group index */
583 uint32_t hw_index; /* h/w ring index */
584 uint32_t intr_vector; /* Interrupt vector index */
585 uint32_t vect_bit; /* vector's bit in register */
586
587 ixgbe_rx_data_t *rx_data; /* Rx software ring */
588
589 kmutex_t rx_lock; /* Rx access lock */
590
591 uint32_t stat_frame_error;
592 uint32_t stat_cksum_error;
593 uint32_t stat_exceed_pkt;
594
595 uint64_t stat_rbytes;
596 uint64_t stat_ipackets;
597
598 mac_ring_handle_t ring_handle;
599 uint64_t ring_gen_num;
600
601 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
602 } ixgbe_rx_ring_t;
603
604 /*
605 * Software Receive Ring Group
606 */
607 typedef struct ixgbe_rx_group {
608 uint32_t index; /* Group index */
609 mac_group_handle_t group_handle; /* call back group handle */
610 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
611 boolean_t aupe; /* AUPE bit */
612 list_t vlans; /* list of VLANs to allow */
613 } ixgbe_rx_group_t;
614
615 /*
616 * structure to map interrupt cleanup to msi-x vector
617 */
618 typedef struct ixgbe_intr_vector {
619 struct ixgbe *ixgbe; /* point to my adapter */
620 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
621 int rxr_cnt; /* count rx rings */
622 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
623 int txr_cnt; /* count tx rings */
624 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
625 int other_cnt; /* count other interrupt */
626 } ixgbe_intr_vector_t;
627
628 /*
629 * Software adapter state
630 */
631 typedef struct ixgbe {
632 int instance;
633 mac_handle_t mac_hdl;
634 dev_info_t *dip;
635 struct ixgbe_hw hw;
636 struct ixgbe_osdep osdep;
637
638 adapter_info_t *capab; /* adapter hardware capabilities */
639 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
640 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
641 ddi_taskq_t *phy_taskq; /* external PHY taskq */
642 uint32_t eims; /* interrupt mask setting */
643 uint32_t eimc; /* interrupt mask clear */
644 uint32_t eicr; /* interrupt cause reg */
645
646 uint32_t ixgbe_state;
647 link_state_t link_state;
648 uint32_t link_speed;
649 uint32_t link_duplex;
650
651 uint32_t reset_count;
652 uint32_t attach_progress;
653 uint32_t loopback_mode;
654 uint32_t default_mtu;
655 uint32_t max_frame_size;
656 ixgbe_link_speed speeds_supported;
657
658 uint32_t rcb_pending;
659
660 /*
661 * Each msi-x vector: map vector to interrupt cleanup
662 */
663 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
664
665 /*
666 * Receive Rings
667 */
668 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
669 uint32_t num_rx_rings; /* Number of rx rings in use */
670 uint32_t rx_ring_size; /* Rx descriptor ring size */
671 uint32_t rx_buf_size; /* Rx buffer size */
672 boolean_t lro_enable; /* Large Receive Offload */
673 uint64_t lro_pkt_count; /* LRO packet count */
674 /*
675 * Receive Groups
676 */
677 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
678 uint32_t num_rx_groups; /* Number of rx groups in use */
679 uint32_t rx_def_group; /* Default Rx group index */
680
681 /*
682 * Transmit Rings
683 */
684 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
685 uint32_t num_tx_rings; /* Number of tx rings in use */
686 uint32_t tx_ring_size; /* Tx descriptor ring size */
687 uint32_t tx_buf_size; /* Tx buffer size */
688
689 boolean_t tx_ring_init;
690 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
691 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
692 boolean_t lso_enable; /* Large Segment Offload */
693 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
694 boolean_t relax_order_enable; /* Relax Order */
695 uint32_t classify_mode; /* Classification mode */
696 uint32_t tx_copy_thresh; /* Tx copy threshold */
697 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
698 uint32_t tx_overload_thresh; /* Tx overload threshold */
699 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
700 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
701 uint32_t rx_copy_thresh; /* Rx copy threshold */
702 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
703 uint32_t intr_throttling[MAX_INTR_VECTOR];
704 uint32_t intr_force;
705 int fm_capabilities; /* FMA capabilities */
706
707 int intr_type;
708 int intr_cnt;
709 uint32_t intr_cnt_max;
710 uint32_t intr_cnt_min;
711 int intr_cap;
712 size_t intr_size;
713 uint_t intr_pri;
714 ddi_intr_handle_t *htable;
715 uint32_t eims_mask;
716 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
717
718 kmutex_t gen_lock; /* General lock for device access */
719 kmutex_t watchdog_lock;
720 kmutex_t rx_pending_lock;
721
722 boolean_t watchdog_enable;
723 boolean_t watchdog_start;
724 timeout_id_t watchdog_tid;
725
726 boolean_t unicst_init;
727 uint32_t unicst_avail;
728 uint32_t unicst_total;
729 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
730 uint32_t mcast_count;
731 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
732
733 boolean_t vlft_enabled; /* VLAN filtering enabled? */
734 boolean_t vlft_init; /* VLAN filtering initialized? */
735
736 ulong_t sys_page_size;
737
738 boolean_t link_check_complete;
739 hrtime_t link_check_hrtime;
740 ddi_periodic_t periodic_id; /* for link check timer func */
741
742 /*
743 * LED related constants.
744 */
745 boolean_t ixgbe_led_active;
746 boolean_t ixgbe_led_blink;
747 uint32_t ixgbe_led_reg;
748 uint32_t ixgbe_led_index;
749
750 /*
751 * Kstat definitions
752 */
753 kstat_t *ixgbe_ks;
754
755 uint32_t param_en_10000fdx_cap:1,
756 param_en_5000fdx_cap:1,
757 param_en_2500fdx_cap:1,
758 param_en_1000fdx_cap:1,
759 param_en_100fdx_cap:1,
760 param_adv_10000fdx_cap:1,
761 param_adv_5000fdx_cap:1,
762 param_adv_2500fdx_cap:1,
763 param_adv_1000fdx_cap:1,
764 param_adv_100fdx_cap:1,
765 param_pause_cap:1,
766 param_asym_pause_cap:1,
767 param_rem_fault:1,
768 param_adv_autoneg_cap:1,
769 param_adv_pause_cap:1,
770 param_adv_asym_pause_cap:1,
771 param_adv_rem_fault:1,
772 param_lp_10000fdx_cap:1,
773 param_lp_5000fdx_cap:1,
774 param_lp_2500fdx_cap:1,
775 param_lp_1000fdx_cap:1,
776 param_lp_100fdx_cap:1,
777 param_lp_autoneg_cap:1,
778 param_lp_pause_cap:1,
779 param_lp_asym_pause_cap:1,
780 param_lp_rem_fault:1,
781 param_pad_to_32:6;
782 } ixgbe_t;
783
784 typedef struct ixgbe_stat {
785 kstat_named_t link_speed; /* Link Speed */
786
787 kstat_named_t reset_count; /* Reset Count */
788
789 kstat_named_t rx_frame_error; /* Rx Error in Packet */
790 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
791 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
792
793 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
794 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
795 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
796 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
797 kstat_named_t tx_reschedule; /* Tx Reschedule */
798 kstat_named_t tx_break_tbd_limit; /* Reached single xmit desc limit */
799 kstat_named_t tx_lso_header_fail; /* New mblk for last LSO hdr frag */
800
801 kstat_named_t gprc; /* Good Packets Received Count */
802 kstat_named_t gptc; /* Good Packets Xmitted Count */
803 kstat_named_t gor; /* Good Octets Received Count */
804 kstat_named_t got; /* Good Octets Xmitd Count */
805 kstat_named_t qor; /* Queue Octets Received */
806 kstat_named_t qot; /* Queue Octets Transmitted */
807 kstat_named_t qpr; /* Queue Packets Received */
808 kstat_named_t qpt; /* Queue Packets Transmitted */
809 kstat_named_t prc64; /* Packets Received - 64b */
810 kstat_named_t prc127; /* Packets Received - 65-127b */
811 kstat_named_t prc255; /* Packets Received - 127-255b */
812 kstat_named_t prc511; /* Packets Received - 256-511b */
813 kstat_named_t prc1023; /* Packets Received - 511-1023b */
814 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
815 kstat_named_t ptc64; /* Packets Xmitted (64b) */
816 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
817 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
818 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
819 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
820 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
821
822 kstat_named_t crcerrs; /* CRC Error Count */
823 kstat_named_t illerrc; /* Illegal Byte Error Count */
824 kstat_named_t errbc; /* Error Byte Count */
825 kstat_named_t mspdc; /* MAC Short Packet Discard Count */
826 kstat_named_t mpc; /* Missed Packets Count */
827 kstat_named_t mlfc; /* MAC Local Fault Count */
828 kstat_named_t mrfc; /* MAC Remote Fault Count */
829 kstat_named_t rlec; /* Receive Length Error Count */
830 kstat_named_t lxontxc; /* Link XON Transmitted Count */
831 kstat_named_t lxonrxc; /* Link XON Received Count */
832 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
833 kstat_named_t lxoffrxc; /* Link XOFF Received Count */
834 kstat_named_t bprc; /* Broadcasts Pkts Received Count */
835 kstat_named_t mprc; /* Multicast Pkts Received Count */
836 kstat_named_t rnbc; /* Receive No Buffers Count */
837 kstat_named_t ruc; /* Receive Undersize Count */
838 kstat_named_t rfc; /* Receive Frag Count */
839 kstat_named_t roc; /* Receive Oversize Count */
840 kstat_named_t rjc; /* Receive Jabber Count */
841 kstat_named_t tor; /* Total Octets Recvd Count */
842 kstat_named_t tot; /* Total Octets Xmitted Count */
843 kstat_named_t tpr; /* Total Packets Received */
844 kstat_named_t tpt; /* Total Packets Xmitted */
845 kstat_named_t mptc; /* Multicast Packets Xmited Count */
846 kstat_named_t bptc; /* Broadcast Packets Xmited Count */
847 kstat_named_t lroc; /* LRO Packets Received Count */
848 kstat_named_t dev_gone; /* Number of device gone events encountered */
849 } ixgbe_stat_t;
850
851 /*
852 * Function prototypes in ixgbe_buf.c
853 */
854 int ixgbe_alloc_dma(ixgbe_t *);
855 void ixgbe_free_dma(ixgbe_t *);
856 void ixgbe_set_fma_flags(int);
857 void ixgbe_free_dma_buffer(dma_buffer_t *);
858 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
859 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
860
861 /*
862 * Function prototypes in ixgbe_main.c
863 */
864 int ixgbe_start(ixgbe_t *, boolean_t);
865 void ixgbe_stop(ixgbe_t *, boolean_t);
866 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
867 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
868 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
869 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
870
871 void ixgbe_enable_watchdog_timer(ixgbe_t *);
872 void ixgbe_disable_watchdog_timer(ixgbe_t *);
873 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
874
875 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
876 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
877 void ixgbe_fm_ereport(ixgbe_t *, char *);
878
879 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
880 mac_ring_info_t *, mac_ring_handle_t);
881 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
882 mac_group_info_t *, mac_group_handle_t);
883 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
884 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
885
886 int ixgbe_transceiver_info(void *, uint_t, mac_transceiver_info_t *);
887 int ixgbe_transceiver_read(void *, uint_t, uint_t, void *, size_t, off_t,
888 size_t *);
889
890 /*
891 * Function prototypes in ixgbe_gld.c
892 */
893 int ixgbe_m_start(void *);
894 void ixgbe_m_stop(void *);
895 int ixgbe_m_promisc(void *, boolean_t);
896 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
897 void ixgbe_m_resources(void *);
898 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
899 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
900 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
901 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
902 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
903 mac_prop_info_handle_t);
904 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
905 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
906 boolean_t ixgbe_param_locked(mac_prop_id_t);
907
908 /*
909 * Function prototypes in ixgbe_rx.c
910 */
911 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
912 void ixgbe_rx_recycle(caddr_t arg);
913 mblk_t *ixgbe_ring_rx_poll(void *, int);
914
915 /*
916 * Function prototypes in ixgbe_tx.c
917 */
918 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
919 void ixgbe_free_tcb(tx_control_block_t *);
920 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
921 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
922 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
923
924 /*
925 * Function prototypes in ixgbe_log.c
926 */
927 void ixgbe_notice(void *, const char *, ...);
928 void ixgbe_log(void *, const char *, ...);
929 void ixgbe_error(void *, const char *, ...);
930
931 /*
932 * Function prototypes in ixgbe_stat.c
933 */
934 int ixgbe_init_stats(ixgbe_t *);
935 int ixgbe_m_stat(void *, uint_t, uint64_t *);
936 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
937 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
938
939 #ifdef __cplusplus
940 }
941 #endif
942
943 #endif /* _IXGBE_SW_H */