74 #include <sys/fm/util.h>
75 #include <sys/disp.h>
76 #include <sys/fm/io/ddi.h>
77 #include "ixgbe_api.h"
78
79 #define MODULE_NAME "ixgbe" /* module name */
80
81 #define IXGBE_FAILURE DDI_FAILURE
82
83 #define IXGBE_UNKNOWN 0x00
84 #define IXGBE_INITIALIZED 0x01
85 #define IXGBE_STARTED 0x02
86 #define IXGBE_SUSPENDED 0x04
87 #define IXGBE_STALL 0x08
88 #define IXGBE_OVERTEMP 0x20
89 #define IXGBE_INTR_ADJUST 0x40
90 #define IXGBE_ERROR 0x80
91
92 #define MAX_NUM_UNICAST_ADDRESSES 0x80
93 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
94 #define IXGBE_INTR_NONE 0
95 #define IXGBE_INTR_MSIX 1
96 #define IXGBE_INTR_MSI 2
97 #define IXGBE_INTR_LEGACY 3
98
99 #define IXGBE_POLL_NULL -1
100
101 #define MAX_COOKIE 18
102 #define MIN_NUM_TX_DESC 2
103
104 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
105
106 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
107
108 #define IXGBE_RX_STOPPED 0x1
109
110 #define IXGBE_PKG_BUF_16k 16384
111
112 /*
113 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
370 * Property lookups
371 */
372 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
373 DDI_PROP_DONTPASS, (n))
374 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
375 DDI_PROP_DONTPASS, (n), -1)
376
377
378 typedef union ixgbe_ether_addr {
379 struct {
380 uint32_t high;
381 uint32_t low;
382 } reg;
383 struct {
384 uint8_t set;
385 uint8_t group_index;
386 uint8_t addr[ETHERADDRL];
387 } mac;
388 } ixgbe_ether_addr_t;
389
390 typedef enum {
391 USE_NONE,
392 USE_COPY,
393 USE_DMA
394 } tx_type_t;
395
396 typedef struct ixgbe_tx_context {
397 uint32_t hcksum_flags;
398 uint32_t ip_hdr_len;
399 uint32_t mac_hdr_len;
400 uint32_t l4_proto;
401 uint32_t mss;
402 uint32_t l4_hdr_len;
403 boolean_t lso_flag;
404 } ixgbe_tx_context_t;
405
406 /*
407 * Hold address/length of each DMA segment
408 */
409 typedef struct sw_desc {
572 uint32_t hw_index; /* h/w ring index */
573 uint32_t intr_vector; /* Interrupt vector index */
574 uint32_t vect_bit; /* vector's bit in register */
575
576 ixgbe_rx_data_t *rx_data; /* Rx software ring */
577
578 kmutex_t rx_lock; /* Rx access lock */
579
580 uint32_t stat_frame_error;
581 uint32_t stat_cksum_error;
582 uint32_t stat_exceed_pkt;
583
584 uint64_t stat_rbytes;
585 uint64_t stat_ipackets;
586
587 mac_ring_handle_t ring_handle;
588 uint64_t ring_gen_num;
589
590 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
591 } ixgbe_rx_ring_t;
592 /*
593 * Software Receive Ring Group
594 */
595 typedef struct ixgbe_rx_group {
596 uint32_t index; /* Group index */
597 mac_group_handle_t group_handle; /* call back group handle */
598 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
599 } ixgbe_rx_group_t;
600
601 /*
602 * structure to map interrupt cleanup to msi-x vector
603 */
604 typedef struct ixgbe_intr_vector {
605 struct ixgbe *ixgbe; /* point to my adapter */
606 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
607 int rxr_cnt; /* count rx rings */
608 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
609 int txr_cnt; /* count tx rings */
610 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
611 int other_cnt; /* count other interrupt */
612 } ixgbe_intr_vector_t;
613
614 /*
615 * Software adapter state
616 */
617 typedef struct ixgbe {
618 int instance;
645
646 /*
647 * Each msi-x vector: map vector to interrupt cleanup
648 */
649 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
650
651 /*
652 * Receive Rings
653 */
654 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
655 uint32_t num_rx_rings; /* Number of rx rings in use */
656 uint32_t rx_ring_size; /* Rx descriptor ring size */
657 uint32_t rx_buf_size; /* Rx buffer size */
658 boolean_t lro_enable; /* Large Receive Offload */
659 uint64_t lro_pkt_count; /* LRO packet count */
660 /*
661 * Receive Groups
662 */
663 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
664 uint32_t num_rx_groups; /* Number of rx groups in use */
665
666 /*
667 * Transmit Rings
668 */
669 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
670 uint32_t num_tx_rings; /* Number of tx rings in use */
671 uint32_t tx_ring_size; /* Tx descriptor ring size */
672 uint32_t tx_buf_size; /* Tx buffer size */
673
674 boolean_t tx_ring_init;
675 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
676 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
677 boolean_t lso_enable; /* Large Segment Offload */
678 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
679 boolean_t relax_order_enable; /* Relax Order */
680 uint32_t classify_mode; /* Classification mode */
681 uint32_t tx_copy_thresh; /* Tx copy threshold */
682 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
683 uint32_t tx_overload_thresh; /* Tx overload threshold */
684 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
698 uint_t intr_pri;
699 ddi_intr_handle_t *htable;
700 uint32_t eims_mask;
701 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
702
703 kmutex_t gen_lock; /* General lock for device access */
704 kmutex_t watchdog_lock;
705 kmutex_t rx_pending_lock;
706
707 boolean_t watchdog_enable;
708 boolean_t watchdog_start;
709 timeout_id_t watchdog_tid;
710
711 boolean_t unicst_init;
712 uint32_t unicst_avail;
713 uint32_t unicst_total;
714 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
715 uint32_t mcast_count;
716 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
717
718 ulong_t sys_page_size;
719
720 boolean_t link_check_complete;
721 hrtime_t link_check_hrtime;
722 ddi_periodic_t periodic_id; /* for link check timer func */
723
724 /*
725 * LED related constants.
726 */
727 boolean_t ixgbe_led_active;
728 boolean_t ixgbe_led_blink;
729 uint32_t ixgbe_led_reg;
730 uint32_t ixgbe_led_index;
731
732 /*
733 * Kstat definitions
734 */
735 kstat_t *ixgbe_ks;
736
737 uint32_t param_en_10000fdx_cap:1,
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74 #include <sys/fm/util.h>
75 #include <sys/disp.h>
76 #include <sys/fm/io/ddi.h>
77 #include "ixgbe_api.h"
78
79 #define MODULE_NAME "ixgbe" /* module name */
80
81 #define IXGBE_FAILURE DDI_FAILURE
82
83 #define IXGBE_UNKNOWN 0x00
84 #define IXGBE_INITIALIZED 0x01
85 #define IXGBE_STARTED 0x02
86 #define IXGBE_SUSPENDED 0x04
87 #define IXGBE_STALL 0x08
88 #define IXGBE_OVERTEMP 0x20
89 #define IXGBE_INTR_ADJUST 0x40
90 #define IXGBE_ERROR 0x80
91
92 #define MAX_NUM_UNICAST_ADDRESSES 0x80
93 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
94 #define MAX_NUM_VLAN_FILTERS 0x40
95
96 #define IXGBE_INTR_NONE 0
97 #define IXGBE_INTR_MSIX 1
98 #define IXGBE_INTR_MSI 2
99 #define IXGBE_INTR_LEGACY 3
100
101 #define IXGBE_POLL_NULL -1
102
103 #define MAX_COOKIE 18
104 #define MIN_NUM_TX_DESC 2
105
106 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
107
108 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
109
110 #define IXGBE_RX_STOPPED 0x1
111
112 #define IXGBE_PKG_BUF_16k 16384
113
114 /*
115 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
372 * Property lookups
373 */
374 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
375 DDI_PROP_DONTPASS, (n))
376 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
377 DDI_PROP_DONTPASS, (n), -1)
378
379
380 typedef union ixgbe_ether_addr {
381 struct {
382 uint32_t high;
383 uint32_t low;
384 } reg;
385 struct {
386 uint8_t set;
387 uint8_t group_index;
388 uint8_t addr[ETHERADDRL];
389 } mac;
390 } ixgbe_ether_addr_t;
391
392 /*
393 * The list of VLANs an Rx group will accept.
394 */
395 typedef struct ixgbe_vlan {
396 list_node_t ixvl_link;
397 uint16_t ixvl_vid; /* The VLAN ID */
398 uint_t ixvl_refs; /* Number of users of this VLAN */
399 } ixgbe_vlan_t;
400
401 typedef enum {
402 USE_NONE,
403 USE_COPY,
404 USE_DMA
405 } tx_type_t;
406
407 typedef struct ixgbe_tx_context {
408 uint32_t hcksum_flags;
409 uint32_t ip_hdr_len;
410 uint32_t mac_hdr_len;
411 uint32_t l4_proto;
412 uint32_t mss;
413 uint32_t l4_hdr_len;
414 boolean_t lso_flag;
415 } ixgbe_tx_context_t;
416
417 /*
418 * Hold address/length of each DMA segment
419 */
420 typedef struct sw_desc {
583 uint32_t hw_index; /* h/w ring index */
584 uint32_t intr_vector; /* Interrupt vector index */
585 uint32_t vect_bit; /* vector's bit in register */
586
587 ixgbe_rx_data_t *rx_data; /* Rx software ring */
588
589 kmutex_t rx_lock; /* Rx access lock */
590
591 uint32_t stat_frame_error;
592 uint32_t stat_cksum_error;
593 uint32_t stat_exceed_pkt;
594
595 uint64_t stat_rbytes;
596 uint64_t stat_ipackets;
597
598 mac_ring_handle_t ring_handle;
599 uint64_t ring_gen_num;
600
601 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
602 } ixgbe_rx_ring_t;
603
604 /*
605 * Software Receive Ring Group
606 */
607 typedef struct ixgbe_rx_group {
608 uint32_t index; /* Group index */
609 mac_group_handle_t group_handle; /* call back group handle */
610 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
611 boolean_t aupe; /* AUPE bit */
612 list_t vlans; /* list of VLANs to allow */
613 } ixgbe_rx_group_t;
614
615 /*
616 * structure to map interrupt cleanup to msi-x vector
617 */
618 typedef struct ixgbe_intr_vector {
619 struct ixgbe *ixgbe; /* point to my adapter */
620 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
621 int rxr_cnt; /* count rx rings */
622 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
623 int txr_cnt; /* count tx rings */
624 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
625 int other_cnt; /* count other interrupt */
626 } ixgbe_intr_vector_t;
627
628 /*
629 * Software adapter state
630 */
631 typedef struct ixgbe {
632 int instance;
659
660 /*
661 * Each msi-x vector: map vector to interrupt cleanup
662 */
663 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
664
665 /*
666 * Receive Rings
667 */
668 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
669 uint32_t num_rx_rings; /* Number of rx rings in use */
670 uint32_t rx_ring_size; /* Rx descriptor ring size */
671 uint32_t rx_buf_size; /* Rx buffer size */
672 boolean_t lro_enable; /* Large Receive Offload */
673 uint64_t lro_pkt_count; /* LRO packet count */
674 /*
675 * Receive Groups
676 */
677 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
678 uint32_t num_rx_groups; /* Number of rx groups in use */
679 uint32_t rx_def_group; /* Default Rx group index */
680
681 /*
682 * Transmit Rings
683 */
684 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
685 uint32_t num_tx_rings; /* Number of tx rings in use */
686 uint32_t tx_ring_size; /* Tx descriptor ring size */
687 uint32_t tx_buf_size; /* Tx buffer size */
688
689 boolean_t tx_ring_init;
690 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
691 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
692 boolean_t lso_enable; /* Large Segment Offload */
693 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
694 boolean_t relax_order_enable; /* Relax Order */
695 uint32_t classify_mode; /* Classification mode */
696 uint32_t tx_copy_thresh; /* Tx copy threshold */
697 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
698 uint32_t tx_overload_thresh; /* Tx overload threshold */
699 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
713 uint_t intr_pri;
714 ddi_intr_handle_t *htable;
715 uint32_t eims_mask;
716 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
717
718 kmutex_t gen_lock; /* General lock for device access */
719 kmutex_t watchdog_lock;
720 kmutex_t rx_pending_lock;
721
722 boolean_t watchdog_enable;
723 boolean_t watchdog_start;
724 timeout_id_t watchdog_tid;
725
726 boolean_t unicst_init;
727 uint32_t unicst_avail;
728 uint32_t unicst_total;
729 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
730 uint32_t mcast_count;
731 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
732
733 boolean_t vlft_enabled; /* VLAN filtering enabled? */
734 boolean_t vlft_init; /* VLAN filtering initialized? */
735
736 ulong_t sys_page_size;
737
738 boolean_t link_check_complete;
739 hrtime_t link_check_hrtime;
740 ddi_periodic_t periodic_id; /* for link check timer func */
741
742 /*
743 * LED related constants.
744 */
745 boolean_t ixgbe_led_active;
746 boolean_t ixgbe_led_blink;
747 uint32_t ixgbe_led_reg;
748 uint32_t ixgbe_led_index;
749
750 /*
751 * Kstat definitions
752 */
753 kstat_t *ixgbe_ks;
754
755 uint32_t param_en_10000fdx_cap:1,
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