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11490 SRS ring polling disabled for VLANs
11491 Want DLS bypass for VLAN traffic
11492 add VLVF bypass to ixgbe core
2869 duplicate packets with vnics over aggrs
11489 DLS stat delete and aggr kstat can deadlock
Portions contributed by: Theo Schlossnagle <jesus@omniti.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Dan McDonald <danmcd@joyent.com>
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_sw.h
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_sw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 30 * Copyright 2019 Joyent, Inc.
31 31 */
32 32
33 33 #ifndef _IXGBE_SW_H
34 34 #define _IXGBE_SW_H
35 35
36 36 #ifdef __cplusplus
37 37 extern "C" {
38 38 #endif
39 39
40 40 #include <sys/types.h>
41 41 #include <sys/conf.h>
42 42 #include <sys/debug.h>
43 43 #include <sys/stropts.h>
44 44 #include <sys/stream.h>
45 45 #include <sys/strsun.h>
46 46 #include <sys/strlog.h>
47 47 #include <sys/kmem.h>
48 48 #include <sys/stat.h>
49 49 #include <sys/kstat.h>
50 50 #include <sys/modctl.h>
51 51 #include <sys/errno.h>
52 52 #include <sys/dlpi.h>
53 53 #include <sys/mac_provider.h>
54 54 #include <sys/mac_ether.h>
55 55 #include <sys/vlan.h>
56 56 #include <sys/ddi.h>
57 57 #include <sys/sunddi.h>
58 58 #include <sys/pci.h>
59 59 #include <sys/pcie.h>
60 60 #include <sys/sdt.h>
61 61 #include <sys/ethernet.h>
62 62 #include <sys/pattr.h>
63 63 #include <sys/strsubr.h>
64 64 #include <sys/netlb.h>
65 65 #include <sys/random.h>
66 66 #include <inet/common.h>
67 67 #include <inet/tcp.h>
68 68 #include <inet/ip.h>
69 69 #include <inet/mi.h>
70 70 #include <inet/nd.h>
71 71 #include <sys/bitmap.h>
72 72 #include <sys/ddifm.h>
73 73 #include <sys/fm/protocol.h>
74 74 #include <sys/fm/util.h>
75 75 #include <sys/disp.h>
76 76 #include <sys/fm/io/ddi.h>
77 77 #include "ixgbe_api.h"
78 78
79 79 #define MODULE_NAME "ixgbe" /* module name */
80 80
81 81 #define IXGBE_FAILURE DDI_FAILURE
82 82
83 83 #define IXGBE_UNKNOWN 0x00
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84 84 #define IXGBE_INITIALIZED 0x01
85 85 #define IXGBE_STARTED 0x02
86 86 #define IXGBE_SUSPENDED 0x04
87 87 #define IXGBE_STALL 0x08
88 88 #define IXGBE_OVERTEMP 0x20
89 89 #define IXGBE_INTR_ADJUST 0x40
90 90 #define IXGBE_ERROR 0x80
91 91
92 92 #define MAX_NUM_UNICAST_ADDRESSES 0x80
93 93 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
94 +#define MAX_NUM_VLAN_FILTERS 0x40
95 +
94 96 #define IXGBE_INTR_NONE 0
95 97 #define IXGBE_INTR_MSIX 1
96 98 #define IXGBE_INTR_MSI 2
97 99 #define IXGBE_INTR_LEGACY 3
98 100
99 101 #define IXGBE_POLL_NULL -1
100 102
101 103 #define MAX_COOKIE 18
102 104 #define MIN_NUM_TX_DESC 2
103 105
104 106 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
105 107
106 108 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
107 109
108 110 #define IXGBE_RX_STOPPED 0x1
109 111
110 112 #define IXGBE_PKG_BUF_16k 16384
111 113
112 114 /*
113 115 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
114 116 * supported silicon types.
115 117 */
116 118 #define MAX_TX_QUEUE_NUM 128
117 119 #define MAX_RX_QUEUE_NUM 128
118 120 #define MAX_INTR_VECTOR 64
119 121
120 122 /*
121 123 * Maximum values for user configurable parameters
122 124 */
123 125 #define MAX_TX_RING_SIZE 4096
124 126 #define MAX_RX_RING_SIZE 4096
125 127
126 128 #define MAX_RX_LIMIT_PER_INTR 4096
127 129
128 130 #define MAX_RX_COPY_THRESHOLD 9216
129 131 #define MAX_TX_COPY_THRESHOLD 9216
130 132 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
131 133 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
132 134 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
133 135
134 136 /*
135 137 * Minimum values for user configurable parameters
136 138 */
137 139 #define MIN_TX_RING_SIZE 64
138 140 #define MIN_RX_RING_SIZE 64
139 141
140 142 #define MIN_MTU ETHERMIN
141 143 #define MIN_RX_LIMIT_PER_INTR 16
142 144 #define MIN_TX_COPY_THRESHOLD 0
143 145 #define MIN_RX_COPY_THRESHOLD 0
144 146 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
145 147 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
146 148 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
147 149
148 150 /*
149 151 * Default values for user configurable parameters
150 152 */
151 153 #define DEFAULT_TX_RING_SIZE 1024
152 154 #define DEFAULT_RX_RING_SIZE 1024
153 155
154 156 #define DEFAULT_MTU ETHERMTU
155 157 #define DEFAULT_RX_LIMIT_PER_INTR 256
156 158 #define DEFAULT_RX_COPY_THRESHOLD 128
157 159 #define DEFAULT_TX_COPY_THRESHOLD 512
158 160 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
159 161 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
160 162 #define DEFAULT_TX_RESCHED_THRESHOLD 128
161 163 #define DEFAULT_FCRTH 0x20000
162 164 #define DEFAULT_FCRTL 0x10000
163 165 #define DEFAULT_FCPAUSE 0xFFFF
164 166
165 167 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
166 168 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
167 169 #define DEFAULT_LSO_ENABLE B_TRUE
168 170 #define DEFAULT_LRO_ENABLE B_FALSE
169 171 #define DEFAULT_MR_ENABLE B_TRUE
170 172 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
171 173 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
172 174 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
173 175
174 176 #define IXGBE_LSO_MAXLEN 65535
175 177
176 178 #define TX_DRAIN_TIME 200
177 179 #define RX_DRAIN_TIME 200
178 180
179 181 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
180 182 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
181 183
182 184 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
183 185
184 186 /*
185 187 * Extra register bit masks for 82598
186 188 */
187 189 #define IXGBE_PCS1GANA_FDC 0x20
188 190 #define IXGBE_PCS1GANLP_LPFD 0x20
189 191 #define IXGBE_PCS1GANLP_LPHD 0x40
190 192
191 193 /*
192 194 * Defined for IP header alignment.
193 195 */
194 196 #define IPHDR_ALIGN_ROOM 2
195 197
196 198 /*
197 199 * Bit flags for attach_progress
198 200 */
199 201 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
200 202 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
201 203 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
202 204 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
203 205 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
204 206 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
205 207 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
206 208 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
207 209 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
208 210 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
209 211 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
210 212 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
211 213 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
212 214 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
213 215 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
214 216 #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
215 217
216 218 #define PROP_DEFAULT_MTU "default_mtu"
217 219 #define PROP_FLOW_CONTROL "flow_control"
218 220 #define PROP_TX_QUEUE_NUM "tx_queue_number"
219 221 #define PROP_TX_RING_SIZE "tx_ring_size"
220 222 #define PROP_RX_QUEUE_NUM "rx_queue_number"
221 223 #define PROP_RX_RING_SIZE "rx_ring_size"
222 224 #define PROP_RX_GROUP_NUM "rx_group_number"
223 225
224 226 #define PROP_INTR_FORCE "intr_force"
225 227 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
226 228 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
227 229 #define PROP_LSO_ENABLE "lso_enable"
228 230 #define PROP_LRO_ENABLE "lro_enable"
229 231 #define PROP_MR_ENABLE "mr_enable"
230 232 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
231 233 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
232 234 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
233 235 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
234 236 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
235 237 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
236 238 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
237 239 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
238 240 #define PROP_INTR_THROTTLING "intr_throttling"
239 241 #define PROP_FM_CAPABLE "fm_capable"
240 242 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
241 243
242 244 #define IXGBE_LB_NONE 0
243 245 #define IXGBE_LB_EXTERNAL 1
244 246 #define IXGBE_LB_INTERNAL_MAC 2
245 247 #define IXGBE_LB_INTERNAL_PHY 3
246 248 #define IXGBE_LB_INTERNAL_SERDES 4
247 249
248 250 /*
249 251 * capability/feature flags
250 252 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
251 253 * Separately, the flag named _ENABLED is set when the feature is enabled.
252 254 */
253 255 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
254 256 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
255 257 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
256 258 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
257 259 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
258 260 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
259 261 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
260 262 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
261 263 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
262 264 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
263 265 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
264 266 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
265 267
266 268 /*
267 269 * Classification mode
268 270 */
269 271 #define IXGBE_CLASSIFY_NONE 0
270 272 #define IXGBE_CLASSIFY_RSS 1
271 273 #define IXGBE_CLASSIFY_VMDQ 2
272 274 #define IXGBE_CLASSIFY_VMDQ_RSS 3
273 275
274 276 /* adapter-specific info for each supported device type */
275 277 typedef struct adapter_info {
276 278 uint32_t max_rx_que_num; /* maximum number of rx queues */
277 279 uint32_t min_rx_que_num; /* minimum number of rx queues */
278 280 uint32_t def_rx_que_num; /* default number of rx queues */
279 281 uint32_t max_rx_grp_num; /* maximum number of rx groups */
280 282 uint32_t min_rx_grp_num; /* minimum number of rx groups */
281 283 uint32_t def_rx_grp_num; /* default number of rx groups */
282 284 uint32_t max_tx_que_num; /* maximum number of tx queues */
283 285 uint32_t min_tx_que_num; /* minimum number of tx queues */
284 286 uint32_t def_tx_que_num; /* default number of tx queues */
285 287 uint32_t max_mtu; /* maximum MTU size */
286 288 /*
287 289 * Interrupt throttling is in unit of 256 nsec
288 290 */
289 291 uint32_t max_intr_throttle; /* maximum interrupt throttle */
290 292 uint32_t min_intr_throttle; /* minimum interrupt throttle */
291 293 uint32_t def_intr_throttle; /* default interrupt throttle */
292 294
293 295 uint32_t max_msix_vect; /* maximum total msix vectors */
294 296 uint32_t max_ring_vect; /* maximum number of ring vectors */
295 297 uint32_t max_other_vect; /* maximum number of other vectors */
296 298 uint32_t other_intr; /* "other" interrupt types handled */
297 299 uint32_t other_gpie; /* "other" interrupt types enabling */
298 300 uint32_t flags; /* capability flags */
299 301 } adapter_info_t;
300 302
301 303 /* bits representing all interrupt types other than tx & rx */
302 304 #define IXGBE_OTHER_INTR 0x3ff00000
303 305 #define IXGBE_82599_OTHER_INTR 0x86100000
304 306
305 307 enum ioc_reply {
306 308 IOC_INVAL = -1, /* bad, NAK with EINVAL */
307 309 IOC_DONE, /* OK, reply sent */
308 310 IOC_ACK, /* OK, just send ACK */
309 311 IOC_REPLY /* OK, just send reply */
310 312 };
311 313
312 314 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
313 315 0, 0, (flag)))
314 316
315 317 /*
316 318 * Defined for ring index operations
317 319 * ASSERT(index < limit)
318 320 * ASSERT(step < limit)
319 321 * ASSERT(index1 < limit)
320 322 * ASSERT(index2 < limit)
321 323 */
322 324 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
323 325 (index) + (step) : (index) + (step) - (limit))
324 326 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
325 327 (index) - (step) : (index) + (limit) - (step))
326 328 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
327 329 (index2) - (index1) : (index2) + (limit) - (index1))
328 330
329 331 #define LINK_LIST_INIT(_LH) \
330 332 (_LH)->head = (_LH)->tail = NULL
331 333
332 334 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
333 335
334 336 #define LIST_POP_HEAD(_LH) \
335 337 (single_link_t *)(_LH)->head; \
336 338 { \
337 339 if ((_LH)->head != NULL) { \
338 340 (_LH)->head = (_LH)->head->link; \
339 341 if ((_LH)->head == NULL) \
340 342 (_LH)->tail = NULL; \
341 343 } \
342 344 }
343 345
344 346 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
345 347
346 348 #define LIST_PUSH_TAIL(_LH, _E) \
347 349 if ((_LH)->tail != NULL) { \
348 350 (_LH)->tail->link = (single_link_t *)(_E); \
349 351 (_LH)->tail = (single_link_t *)(_E); \
350 352 } else { \
351 353 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
352 354 } \
353 355 (_E)->link = NULL;
354 356
355 357 #define LIST_GET_NEXT(_LH, _E) \
356 358 (((_LH)->tail == (single_link_t *)(_E)) ? \
357 359 NULL : ((single_link_t *)(_E))->link)
358 360
359 361
360 362 typedef struct single_link {
361 363 struct single_link *link;
362 364 } single_link_t;
363 365
364 366 typedef struct link_list {
365 367 single_link_t *head;
366 368 single_link_t *tail;
367 369 } link_list_t;
368 370
369 371 /*
370 372 * Property lookups
371 373 */
372 374 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
373 375 DDI_PROP_DONTPASS, (n))
374 376 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
375 377 DDI_PROP_DONTPASS, (n), -1)
376 378
377 379
378 380 typedef union ixgbe_ether_addr {
379 381 struct {
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380 382 uint32_t high;
381 383 uint32_t low;
382 384 } reg;
383 385 struct {
384 386 uint8_t set;
385 387 uint8_t group_index;
386 388 uint8_t addr[ETHERADDRL];
387 389 } mac;
388 390 } ixgbe_ether_addr_t;
389 391
392 +/*
393 + * The list of VLANs an Rx group will accept.
394 + */
395 +typedef struct ixgbe_vlan {
396 + list_node_t ixvl_link;
397 + uint16_t ixvl_vid; /* The VLAN ID */
398 + uint_t ixvl_refs; /* Number of users of this VLAN */
399 +} ixgbe_vlan_t;
400 +
390 401 typedef enum {
391 402 USE_NONE,
392 403 USE_COPY,
393 404 USE_DMA
394 405 } tx_type_t;
395 406
396 407 typedef struct ixgbe_tx_context {
397 408 uint32_t hcksum_flags;
398 409 uint32_t ip_hdr_len;
399 410 uint32_t mac_hdr_len;
400 411 uint32_t l4_proto;
401 412 uint32_t mss;
402 413 uint32_t l4_hdr_len;
403 414 boolean_t lso_flag;
404 415 } ixgbe_tx_context_t;
405 416
406 417 /*
407 418 * Hold address/length of each DMA segment
408 419 */
409 420 typedef struct sw_desc {
410 421 uint64_t address;
411 422 size_t length;
412 423 } sw_desc_t;
413 424
414 425 /*
415 426 * Handles and addresses of DMA buffer
416 427 */
417 428 typedef struct dma_buffer {
418 429 caddr_t address; /* Virtual address */
419 430 uint64_t dma_address; /* DMA (Hardware) address */
420 431 ddi_acc_handle_t acc_handle; /* Data access handle */
421 432 ddi_dma_handle_t dma_handle; /* DMA handle */
422 433 size_t size; /* Buffer size */
423 434 size_t len; /* Data length in the buffer */
424 435 } dma_buffer_t;
425 436
426 437 /*
427 438 * Tx Control Block
428 439 */
429 440 typedef struct tx_control_block {
430 441 single_link_t link;
431 442 uint32_t last_index; /* last descriptor of the pkt */
432 443 uint32_t frag_num;
433 444 uint32_t desc_num;
434 445 mblk_t *mp;
435 446 tx_type_t tx_type;
436 447 ddi_dma_handle_t tx_dma_handle;
437 448 dma_buffer_t tx_buf;
438 449 sw_desc_t desc[MAX_COOKIE];
439 450 } tx_control_block_t;
440 451
441 452 /*
442 453 * RX Control Block
443 454 */
444 455 typedef struct rx_control_block {
445 456 mblk_t *mp;
446 457 uint32_t ref_cnt;
447 458 dma_buffer_t rx_buf;
448 459 frtn_t free_rtn;
449 460 struct ixgbe_rx_data *rx_data;
450 461 int lro_next; /* Index of next rcb */
451 462 int lro_prev; /* Index of previous rcb */
452 463 boolean_t lro_pkt; /* Flag for LRO rcb */
453 464 } rx_control_block_t;
454 465
455 466 /*
456 467 * Software Data Structure for Tx Ring
457 468 */
458 469 typedef struct ixgbe_tx_ring {
459 470 uint32_t index; /* Ring index */
460 471 uint32_t intr_vector; /* Interrupt vector index */
461 472 uint32_t vect_bit; /* vector's bit in register */
462 473
463 474 /*
464 475 * Mutexes
465 476 */
466 477 kmutex_t tx_lock;
467 478 kmutex_t recycle_lock;
468 479 kmutex_t tcb_head_lock;
469 480 kmutex_t tcb_tail_lock;
470 481
471 482 /*
472 483 * Tx descriptor ring definitions
473 484 */
474 485 dma_buffer_t tbd_area;
475 486 union ixgbe_adv_tx_desc *tbd_ring;
476 487 uint32_t tbd_head; /* Index of next tbd to recycle */
477 488 uint32_t tbd_tail; /* Index of next tbd to transmit */
478 489 uint32_t tbd_free; /* Number of free tbd */
479 490
480 491 /*
481 492 * Tx control block list definitions
482 493 */
483 494 tx_control_block_t *tcb_area;
484 495 tx_control_block_t **work_list;
485 496 tx_control_block_t **free_list;
486 497 uint32_t tcb_head; /* Head index of free list */
487 498 uint32_t tcb_tail; /* Tail index of free list */
488 499 uint32_t tcb_free; /* Number of free tcb in free list */
489 500
490 501 uint32_t *tbd_head_wb; /* Head write-back */
491 502 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *);
492 503
493 504 /*
494 505 * s/w context structure for TCP/UDP checksum offload
495 506 * and LSO.
496 507 */
497 508 ixgbe_tx_context_t tx_context;
498 509
499 510 /*
500 511 * Tx ring settings and status
501 512 */
502 513 uint32_t ring_size; /* Tx descriptor ring size */
503 514 uint32_t free_list_size; /* Tx free list size */
504 515
505 516 boolean_t reschedule;
506 517 uint32_t recycle_fail;
507 518 uint32_t stall_watchdog;
508 519
509 520 uint32_t stat_overload;
510 521 uint32_t stat_fail_no_tbd;
511 522 uint32_t stat_fail_no_tcb;
512 523 uint32_t stat_fail_dma_bind;
513 524 uint32_t stat_reschedule;
514 525 uint32_t stat_break_tbd_limit;
515 526 uint32_t stat_lso_header_fail;
516 527
517 528 uint64_t stat_obytes;
518 529 uint64_t stat_opackets;
519 530
520 531 mac_ring_handle_t ring_handle;
521 532
522 533 /*
523 534 * Pointer to the ixgbe struct
524 535 */
525 536 struct ixgbe *ixgbe;
526 537 } ixgbe_tx_ring_t;
527 538
528 539 /*
529 540 * Software Receive Ring
530 541 */
531 542 typedef struct ixgbe_rx_data {
532 543 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
533 544
534 545 /*
535 546 * Rx descriptor ring definitions
536 547 */
537 548 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
538 549 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */
539 550 uint32_t rbd_next; /* Index of next rx desc */
540 551
541 552 /*
542 553 * Rx control block list definitions
543 554 */
544 555 rx_control_block_t *rcb_area;
545 556 rx_control_block_t **work_list; /* Work list of rcbs */
546 557 rx_control_block_t **free_list; /* Free list of rcbs */
547 558 uint32_t rcb_head; /* Index of next free rcb */
548 559 uint32_t rcb_tail; /* Index to put recycled rcb */
549 560 uint32_t rcb_free; /* Number of free rcbs */
550 561
551 562 /*
552 563 * Rx sw ring settings and status
553 564 */
554 565 uint32_t ring_size; /* Rx descriptor ring size */
555 566 uint32_t free_list_size; /* Rx free list size */
556 567
557 568 uint32_t rcb_pending;
558 569 uint32_t flag;
559 570
560 571 uint32_t lro_num; /* Number of rcbs of one LRO */
561 572 uint32_t lro_first; /* Index of first LRO rcb */
562 573
563 574 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */
564 575 } ixgbe_rx_data_t;
565 576
566 577 /*
567 578 * Software Data Structure for Rx Ring
568 579 */
569 580 typedef struct ixgbe_rx_ring {
570 581 uint32_t index; /* Ring index */
571 582 uint32_t group_index; /* Group index */
572 583 uint32_t hw_index; /* h/w ring index */
573 584 uint32_t intr_vector; /* Interrupt vector index */
574 585 uint32_t vect_bit; /* vector's bit in register */
575 586
576 587 ixgbe_rx_data_t *rx_data; /* Rx software ring */
577 588
578 589 kmutex_t rx_lock; /* Rx access lock */
579 590
580 591 uint32_t stat_frame_error;
581 592 uint32_t stat_cksum_error;
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582 593 uint32_t stat_exceed_pkt;
583 594
584 595 uint64_t stat_rbytes;
585 596 uint64_t stat_ipackets;
586 597
587 598 mac_ring_handle_t ring_handle;
588 599 uint64_t ring_gen_num;
589 600
590 601 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
591 602 } ixgbe_rx_ring_t;
603 +
592 604 /*
593 605 * Software Receive Ring Group
594 606 */
595 607 typedef struct ixgbe_rx_group {
596 608 uint32_t index; /* Group index */
597 609 mac_group_handle_t group_handle; /* call back group handle */
598 610 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
611 + boolean_t aupe; /* AUPE bit */
612 + list_t vlans; /* list of VLANs to allow */
599 613 } ixgbe_rx_group_t;
600 614
601 615 /*
602 616 * structure to map interrupt cleanup to msi-x vector
603 617 */
604 618 typedef struct ixgbe_intr_vector {
605 619 struct ixgbe *ixgbe; /* point to my adapter */
606 620 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
607 621 int rxr_cnt; /* count rx rings */
608 622 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
609 623 int txr_cnt; /* count tx rings */
610 624 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
611 625 int other_cnt; /* count other interrupt */
612 626 } ixgbe_intr_vector_t;
613 627
614 628 /*
615 629 * Software adapter state
616 630 */
617 631 typedef struct ixgbe {
618 632 int instance;
619 633 mac_handle_t mac_hdl;
620 634 dev_info_t *dip;
621 635 struct ixgbe_hw hw;
622 636 struct ixgbe_osdep osdep;
623 637
624 638 adapter_info_t *capab; /* adapter hardware capabilities */
625 639 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
626 640 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
627 641 ddi_taskq_t *phy_taskq; /* external PHY taskq */
628 642 uint32_t eims; /* interrupt mask setting */
629 643 uint32_t eimc; /* interrupt mask clear */
630 644 uint32_t eicr; /* interrupt cause reg */
631 645
632 646 uint32_t ixgbe_state;
633 647 link_state_t link_state;
634 648 uint32_t link_speed;
635 649 uint32_t link_duplex;
636 650
637 651 uint32_t reset_count;
638 652 uint32_t attach_progress;
639 653 uint32_t loopback_mode;
640 654 uint32_t default_mtu;
641 655 uint32_t max_frame_size;
642 656 ixgbe_link_speed speeds_supported;
643 657
644 658 uint32_t rcb_pending;
645 659
646 660 /*
647 661 * Each msi-x vector: map vector to interrupt cleanup
648 662 */
649 663 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
650 664
651 665 /*
652 666 * Receive Rings
653 667 */
654 668 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
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655 669 uint32_t num_rx_rings; /* Number of rx rings in use */
656 670 uint32_t rx_ring_size; /* Rx descriptor ring size */
657 671 uint32_t rx_buf_size; /* Rx buffer size */
658 672 boolean_t lro_enable; /* Large Receive Offload */
659 673 uint64_t lro_pkt_count; /* LRO packet count */
660 674 /*
661 675 * Receive Groups
662 676 */
663 677 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
664 678 uint32_t num_rx_groups; /* Number of rx groups in use */
679 + uint32_t rx_def_group; /* Default Rx group index */
665 680
666 681 /*
667 682 * Transmit Rings
668 683 */
669 684 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
670 685 uint32_t num_tx_rings; /* Number of tx rings in use */
671 686 uint32_t tx_ring_size; /* Tx descriptor ring size */
672 687 uint32_t tx_buf_size; /* Tx buffer size */
673 688
674 689 boolean_t tx_ring_init;
675 690 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
676 691 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
677 692 boolean_t lso_enable; /* Large Segment Offload */
678 693 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
679 694 boolean_t relax_order_enable; /* Relax Order */
680 695 uint32_t classify_mode; /* Classification mode */
681 696 uint32_t tx_copy_thresh; /* Tx copy threshold */
682 697 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
683 698 uint32_t tx_overload_thresh; /* Tx overload threshold */
684 699 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
685 700 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
686 701 uint32_t rx_copy_thresh; /* Rx copy threshold */
687 702 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
688 703 uint32_t intr_throttling[MAX_INTR_VECTOR];
689 704 uint32_t intr_force;
690 705 int fm_capabilities; /* FMA capabilities */
691 706
692 707 int intr_type;
693 708 int intr_cnt;
694 709 uint32_t intr_cnt_max;
695 710 uint32_t intr_cnt_min;
696 711 int intr_cap;
697 712 size_t intr_size;
698 713 uint_t intr_pri;
699 714 ddi_intr_handle_t *htable;
700 715 uint32_t eims_mask;
701 716 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
702 717
703 718 kmutex_t gen_lock; /* General lock for device access */
704 719 kmutex_t watchdog_lock;
705 720 kmutex_t rx_pending_lock;
706 721
707 722 boolean_t watchdog_enable;
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708 723 boolean_t watchdog_start;
709 724 timeout_id_t watchdog_tid;
710 725
711 726 boolean_t unicst_init;
712 727 uint32_t unicst_avail;
713 728 uint32_t unicst_total;
714 729 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
715 730 uint32_t mcast_count;
716 731 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
717 732
733 + boolean_t vlft_enabled; /* VLAN filtering enabled? */
734 + boolean_t vlft_init; /* VLAN filtering initialized? */
735 +
718 736 ulong_t sys_page_size;
719 737
720 738 boolean_t link_check_complete;
721 739 hrtime_t link_check_hrtime;
722 740 ddi_periodic_t periodic_id; /* for link check timer func */
723 741
724 742 /*
725 743 * LED related constants.
726 744 */
727 745 boolean_t ixgbe_led_active;
728 746 boolean_t ixgbe_led_blink;
729 747 uint32_t ixgbe_led_reg;
730 748 uint32_t ixgbe_led_index;
731 749
732 750 /*
733 751 * Kstat definitions
734 752 */
735 753 kstat_t *ixgbe_ks;
736 754
737 755 uint32_t param_en_10000fdx_cap:1,
738 756 param_en_5000fdx_cap:1,
739 757 param_en_2500fdx_cap:1,
740 758 param_en_1000fdx_cap:1,
741 759 param_en_100fdx_cap:1,
742 760 param_adv_10000fdx_cap:1,
743 761 param_adv_5000fdx_cap:1,
744 762 param_adv_2500fdx_cap:1,
745 763 param_adv_1000fdx_cap:1,
746 764 param_adv_100fdx_cap:1,
747 765 param_pause_cap:1,
748 766 param_asym_pause_cap:1,
749 767 param_rem_fault:1,
750 768 param_adv_autoneg_cap:1,
751 769 param_adv_pause_cap:1,
752 770 param_adv_asym_pause_cap:1,
753 771 param_adv_rem_fault:1,
754 772 param_lp_10000fdx_cap:1,
755 773 param_lp_5000fdx_cap:1,
756 774 param_lp_2500fdx_cap:1,
757 775 param_lp_1000fdx_cap:1,
758 776 param_lp_100fdx_cap:1,
759 777 param_lp_autoneg_cap:1,
760 778 param_lp_pause_cap:1,
761 779 param_lp_asym_pause_cap:1,
762 780 param_lp_rem_fault:1,
763 781 param_pad_to_32:6;
764 782 } ixgbe_t;
765 783
766 784 typedef struct ixgbe_stat {
767 785 kstat_named_t link_speed; /* Link Speed */
768 786
769 787 kstat_named_t reset_count; /* Reset Count */
770 788
771 789 kstat_named_t rx_frame_error; /* Rx Error in Packet */
772 790 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
773 791 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
774 792
775 793 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
776 794 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
777 795 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
778 796 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
779 797 kstat_named_t tx_reschedule; /* Tx Reschedule */
780 798 kstat_named_t tx_break_tbd_limit; /* Reached single xmit desc limit */
781 799 kstat_named_t tx_lso_header_fail; /* New mblk for last LSO hdr frag */
782 800
783 801 kstat_named_t gprc; /* Good Packets Received Count */
784 802 kstat_named_t gptc; /* Good Packets Xmitted Count */
785 803 kstat_named_t gor; /* Good Octets Received Count */
786 804 kstat_named_t got; /* Good Octets Xmitd Count */
787 805 kstat_named_t qor; /* Queue Octets Received */
788 806 kstat_named_t qot; /* Queue Octets Transmitted */
789 807 kstat_named_t qpr; /* Queue Packets Received */
790 808 kstat_named_t qpt; /* Queue Packets Transmitted */
791 809 kstat_named_t prc64; /* Packets Received - 64b */
792 810 kstat_named_t prc127; /* Packets Received - 65-127b */
793 811 kstat_named_t prc255; /* Packets Received - 127-255b */
794 812 kstat_named_t prc511; /* Packets Received - 256-511b */
795 813 kstat_named_t prc1023; /* Packets Received - 511-1023b */
796 814 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
797 815 kstat_named_t ptc64; /* Packets Xmitted (64b) */
798 816 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
799 817 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
800 818 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
801 819 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
802 820 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
803 821
804 822 kstat_named_t crcerrs; /* CRC Error Count */
805 823 kstat_named_t illerrc; /* Illegal Byte Error Count */
806 824 kstat_named_t errbc; /* Error Byte Count */
807 825 kstat_named_t mspdc; /* MAC Short Packet Discard Count */
808 826 kstat_named_t mpc; /* Missed Packets Count */
809 827 kstat_named_t mlfc; /* MAC Local Fault Count */
810 828 kstat_named_t mrfc; /* MAC Remote Fault Count */
811 829 kstat_named_t rlec; /* Receive Length Error Count */
812 830 kstat_named_t lxontxc; /* Link XON Transmitted Count */
813 831 kstat_named_t lxonrxc; /* Link XON Received Count */
814 832 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
815 833 kstat_named_t lxoffrxc; /* Link XOFF Received Count */
816 834 kstat_named_t bprc; /* Broadcasts Pkts Received Count */
817 835 kstat_named_t mprc; /* Multicast Pkts Received Count */
818 836 kstat_named_t rnbc; /* Receive No Buffers Count */
819 837 kstat_named_t ruc; /* Receive Undersize Count */
820 838 kstat_named_t rfc; /* Receive Frag Count */
821 839 kstat_named_t roc; /* Receive Oversize Count */
822 840 kstat_named_t rjc; /* Receive Jabber Count */
823 841 kstat_named_t tor; /* Total Octets Recvd Count */
824 842 kstat_named_t tot; /* Total Octets Xmitted Count */
825 843 kstat_named_t tpr; /* Total Packets Received */
826 844 kstat_named_t tpt; /* Total Packets Xmitted */
827 845 kstat_named_t mptc; /* Multicast Packets Xmited Count */
828 846 kstat_named_t bptc; /* Broadcast Packets Xmited Count */
829 847 kstat_named_t lroc; /* LRO Packets Received Count */
830 848 kstat_named_t dev_gone; /* Number of device gone events encountered */
831 849 } ixgbe_stat_t;
832 850
833 851 /*
834 852 * Function prototypes in ixgbe_buf.c
835 853 */
836 854 int ixgbe_alloc_dma(ixgbe_t *);
837 855 void ixgbe_free_dma(ixgbe_t *);
838 856 void ixgbe_set_fma_flags(int);
839 857 void ixgbe_free_dma_buffer(dma_buffer_t *);
840 858 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
841 859 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
842 860
843 861 /*
844 862 * Function prototypes in ixgbe_main.c
845 863 */
846 864 int ixgbe_start(ixgbe_t *, boolean_t);
847 865 void ixgbe_stop(ixgbe_t *, boolean_t);
848 866 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
849 867 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
850 868 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
851 869 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
852 870
853 871 void ixgbe_enable_watchdog_timer(ixgbe_t *);
854 872 void ixgbe_disable_watchdog_timer(ixgbe_t *);
855 873 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
856 874
857 875 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
858 876 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
859 877 void ixgbe_fm_ereport(ixgbe_t *, char *);
860 878
861 879 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
862 880 mac_ring_info_t *, mac_ring_handle_t);
863 881 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
864 882 mac_group_info_t *, mac_group_handle_t);
865 883 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
866 884 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
867 885
868 886 int ixgbe_transceiver_info(void *, uint_t, mac_transceiver_info_t *);
869 887 int ixgbe_transceiver_read(void *, uint_t, uint_t, void *, size_t, off_t,
870 888 size_t *);
871 889
872 890 /*
873 891 * Function prototypes in ixgbe_gld.c
874 892 */
875 893 int ixgbe_m_start(void *);
876 894 void ixgbe_m_stop(void *);
877 895 int ixgbe_m_promisc(void *, boolean_t);
878 896 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
879 897 void ixgbe_m_resources(void *);
880 898 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
881 899 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
882 900 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
883 901 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
884 902 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
885 903 mac_prop_info_handle_t);
886 904 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
887 905 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
888 906 boolean_t ixgbe_param_locked(mac_prop_id_t);
889 907
890 908 /*
891 909 * Function prototypes in ixgbe_rx.c
892 910 */
893 911 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
894 912 void ixgbe_rx_recycle(caddr_t arg);
895 913 mblk_t *ixgbe_ring_rx_poll(void *, int);
896 914
897 915 /*
898 916 * Function prototypes in ixgbe_tx.c
899 917 */
900 918 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
901 919 void ixgbe_free_tcb(tx_control_block_t *);
902 920 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
903 921 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
904 922 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
905 923
906 924 /*
907 925 * Function prototypes in ixgbe_log.c
908 926 */
909 927 void ixgbe_notice(void *, const char *, ...);
910 928 void ixgbe_log(void *, const char *, ...);
911 929 void ixgbe_error(void *, const char *, ...);
912 930
913 931 /*
914 932 * Function prototypes in ixgbe_stat.c
915 933 */
916 934 int ixgbe_init_stats(ixgbe_t *);
917 935 int ixgbe_m_stat(void *, uint_t, uint64_t *);
918 936 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
919 937 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
920 938
921 939 #ifdef __cplusplus
922 940 }
923 941 #endif
924 942
925 943 #endif /* _IXGBE_SW_H */
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