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12011 ixgbe reports incorrect MAC_STAT_NORCVBUF
Change-Id: Ia71b5669b2bc8f6256a84b0b9c673153f327f5ab
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_main.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 - * Copyright (c) 2017, Joyent, Inc.
28 + * Copyright 2019 Joyent, Inc.
29 29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 30 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
31 31 * Copyright (c) 2013 OSN Online Service Nuernberg GmbH. All rights reserved.
32 32 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
33 33 */
34 34
35 35 #include "ixgbe_sw.h"
36 36
37 37 static char ixgbe_ident[] = "Intel 10Gb Ethernet";
38 38
39 39 /*
40 40 * Local function protoypes
41 41 */
42 42 static int ixgbe_register_mac(ixgbe_t *);
43 43 static int ixgbe_identify_hardware(ixgbe_t *);
44 44 static int ixgbe_regs_map(ixgbe_t *);
45 45 static void ixgbe_init_properties(ixgbe_t *);
46 46 static int ixgbe_init_driver_settings(ixgbe_t *);
47 47 static void ixgbe_init_locks(ixgbe_t *);
48 48 static void ixgbe_destroy_locks(ixgbe_t *);
49 49 static int ixgbe_init(ixgbe_t *);
50 50 static int ixgbe_chip_start(ixgbe_t *);
51 51 static void ixgbe_chip_stop(ixgbe_t *);
52 52 static int ixgbe_reset(ixgbe_t *);
53 53 static void ixgbe_tx_clean(ixgbe_t *);
54 54 static boolean_t ixgbe_tx_drain(ixgbe_t *);
55 55 static boolean_t ixgbe_rx_drain(ixgbe_t *);
56 56 static int ixgbe_alloc_rings(ixgbe_t *);
57 57 static void ixgbe_free_rings(ixgbe_t *);
58 58 static int ixgbe_alloc_rx_data(ixgbe_t *);
59 59 static void ixgbe_free_rx_data(ixgbe_t *);
60 60 static void ixgbe_setup_rings(ixgbe_t *);
61 61 static void ixgbe_setup_rx(ixgbe_t *);
62 62 static void ixgbe_setup_tx(ixgbe_t *);
63 63 static void ixgbe_setup_rx_ring(ixgbe_rx_ring_t *);
64 64 static void ixgbe_setup_tx_ring(ixgbe_tx_ring_t *);
65 65 static void ixgbe_setup_rss(ixgbe_t *);
66 66 static void ixgbe_setup_vmdq(ixgbe_t *);
67 67 static void ixgbe_setup_vmdq_rss(ixgbe_t *);
68 68 static void ixgbe_setup_rss_table(ixgbe_t *);
69 69 static void ixgbe_init_unicst(ixgbe_t *);
70 70 static int ixgbe_unicst_find(ixgbe_t *, const uint8_t *);
71 71 static void ixgbe_setup_multicst(ixgbe_t *);
72 72 static void ixgbe_get_hw_state(ixgbe_t *);
73 73 static void ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe);
74 74 static void ixgbe_get_conf(ixgbe_t *);
75 75 static void ixgbe_init_params(ixgbe_t *);
76 76 static int ixgbe_get_prop(ixgbe_t *, char *, int, int, int);
77 77 static void ixgbe_driver_link_check(ixgbe_t *);
78 78 static void ixgbe_sfp_check(void *);
79 79 static void ixgbe_overtemp_check(void *);
80 80 static void ixgbe_phy_check(void *);
81 81 static void ixgbe_link_timer(void *);
82 82 static void ixgbe_local_timer(void *);
83 83 static void ixgbe_arm_watchdog_timer(ixgbe_t *);
84 84 static void ixgbe_restart_watchdog_timer(ixgbe_t *);
85 85 static void ixgbe_disable_adapter_interrupts(ixgbe_t *);
86 86 static void ixgbe_enable_adapter_interrupts(ixgbe_t *);
87 87 static boolean_t is_valid_mac_addr(uint8_t *);
88 88 static boolean_t ixgbe_stall_check(ixgbe_t *);
89 89 static boolean_t ixgbe_set_loopback_mode(ixgbe_t *, uint32_t);
90 90 static void ixgbe_set_internal_mac_loopback(ixgbe_t *);
91 91 static boolean_t ixgbe_find_mac_address(ixgbe_t *);
92 92 static int ixgbe_alloc_intrs(ixgbe_t *);
93 93 static int ixgbe_alloc_intr_handles(ixgbe_t *, int);
94 94 static int ixgbe_add_intr_handlers(ixgbe_t *);
95 95 static void ixgbe_map_rxring_to_vector(ixgbe_t *, int, int);
96 96 static void ixgbe_map_txring_to_vector(ixgbe_t *, int, int);
97 97 static void ixgbe_setup_ivar(ixgbe_t *, uint16_t, uint8_t, int8_t);
98 98 static void ixgbe_enable_ivar(ixgbe_t *, uint16_t, int8_t);
99 99 static void ixgbe_disable_ivar(ixgbe_t *, uint16_t, int8_t);
100 100 static uint32_t ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index);
101 101 static int ixgbe_map_intrs_to_vectors(ixgbe_t *);
102 102 static void ixgbe_setup_adapter_vector(ixgbe_t *);
103 103 static void ixgbe_rem_intr_handlers(ixgbe_t *);
104 104 static void ixgbe_rem_intrs(ixgbe_t *);
105 105 static int ixgbe_enable_intrs(ixgbe_t *);
106 106 static int ixgbe_disable_intrs(ixgbe_t *);
107 107 static uint_t ixgbe_intr_legacy(void *, void *);
108 108 static uint_t ixgbe_intr_msi(void *, void *);
109 109 static uint_t ixgbe_intr_msix(void *, void *);
110 110 static void ixgbe_intr_rx_work(ixgbe_rx_ring_t *);
111 111 static void ixgbe_intr_tx_work(ixgbe_tx_ring_t *);
112 112 static void ixgbe_intr_other_work(ixgbe_t *, uint32_t);
113 113 static void ixgbe_get_driver_control(struct ixgbe_hw *);
114 114 static int ixgbe_addmac(void *, const uint8_t *);
115 115 static int ixgbe_remmac(void *, const uint8_t *);
116 116 static void ixgbe_release_driver_control(struct ixgbe_hw *);
117 117
118 118 static int ixgbe_attach(dev_info_t *, ddi_attach_cmd_t);
119 119 static int ixgbe_detach(dev_info_t *, ddi_detach_cmd_t);
120 120 static int ixgbe_resume(dev_info_t *);
121 121 static int ixgbe_suspend(dev_info_t *);
122 122 static int ixgbe_quiesce(dev_info_t *);
123 123 static void ixgbe_unconfigure(dev_info_t *, ixgbe_t *);
124 124 static uint8_t *ixgbe_mc_table_itr(struct ixgbe_hw *, uint8_t **, uint32_t *);
125 125 static int ixgbe_cbfunc(dev_info_t *, ddi_cb_action_t, void *, void *, void *);
126 126 static int ixgbe_intr_cb_register(ixgbe_t *);
127 127 static int ixgbe_intr_adjust(ixgbe_t *, ddi_cb_action_t, int);
128 128
129 129 static int ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err,
130 130 const void *impl_data);
131 131 static void ixgbe_fm_init(ixgbe_t *);
132 132 static void ixgbe_fm_fini(ixgbe_t *);
133 133
134 134 char *ixgbe_priv_props[] = {
135 135 "_tx_copy_thresh",
136 136 "_tx_recycle_thresh",
137 137 "_tx_overload_thresh",
138 138 "_tx_resched_thresh",
139 139 "_rx_copy_thresh",
140 140 "_rx_limit_per_intr",
141 141 "_intr_throttling",
142 142 "_adv_pause_cap",
143 143 "_adv_asym_pause_cap",
144 144 NULL
145 145 };
146 146
147 147 #define IXGBE_MAX_PRIV_PROPS \
148 148 (sizeof (ixgbe_priv_props) / sizeof (mac_priv_prop_t))
149 149
150 150 static struct cb_ops ixgbe_cb_ops = {
151 151 nulldev, /* cb_open */
152 152 nulldev, /* cb_close */
153 153 nodev, /* cb_strategy */
154 154 nodev, /* cb_print */
155 155 nodev, /* cb_dump */
156 156 nodev, /* cb_read */
157 157 nodev, /* cb_write */
158 158 nodev, /* cb_ioctl */
159 159 nodev, /* cb_devmap */
160 160 nodev, /* cb_mmap */
161 161 nodev, /* cb_segmap */
162 162 nochpoll, /* cb_chpoll */
163 163 ddi_prop_op, /* cb_prop_op */
164 164 NULL, /* cb_stream */
165 165 D_MP | D_HOTPLUG, /* cb_flag */
166 166 CB_REV, /* cb_rev */
167 167 nodev, /* cb_aread */
168 168 nodev /* cb_awrite */
169 169 };
170 170
171 171 static struct dev_ops ixgbe_dev_ops = {
172 172 DEVO_REV, /* devo_rev */
173 173 0, /* devo_refcnt */
174 174 NULL, /* devo_getinfo */
175 175 nulldev, /* devo_identify */
176 176 nulldev, /* devo_probe */
177 177 ixgbe_attach, /* devo_attach */
178 178 ixgbe_detach, /* devo_detach */
179 179 nodev, /* devo_reset */
180 180 &ixgbe_cb_ops, /* devo_cb_ops */
181 181 NULL, /* devo_bus_ops */
182 182 ddi_power, /* devo_power */
183 183 ixgbe_quiesce, /* devo_quiesce */
184 184 };
185 185
186 186 static struct modldrv ixgbe_modldrv = {
187 187 &mod_driverops, /* Type of module. This one is a driver */
188 188 ixgbe_ident, /* Discription string */
189 189 &ixgbe_dev_ops /* driver ops */
190 190 };
191 191
192 192 static struct modlinkage ixgbe_modlinkage = {
193 193 MODREV_1, &ixgbe_modldrv, NULL
194 194 };
195 195
196 196 /*
197 197 * Access attributes for register mapping
198 198 */
199 199 ddi_device_acc_attr_t ixgbe_regs_acc_attr = {
200 200 DDI_DEVICE_ATTR_V1,
201 201 DDI_STRUCTURE_LE_ACC,
202 202 DDI_STRICTORDER_ACC,
203 203 DDI_FLAGERR_ACC
204 204 };
205 205
206 206 /*
207 207 * Loopback property
208 208 */
209 209 static lb_property_t lb_normal = {
210 210 normal, "normal", IXGBE_LB_NONE
211 211 };
212 212
213 213 static lb_property_t lb_mac = {
214 214 internal, "MAC", IXGBE_LB_INTERNAL_MAC
215 215 };
216 216
217 217 static lb_property_t lb_external = {
218 218 external, "External", IXGBE_LB_EXTERNAL
219 219 };
220 220
221 221 #define IXGBE_M_CALLBACK_FLAGS \
222 222 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
223 223
224 224 static mac_callbacks_t ixgbe_m_callbacks = {
225 225 IXGBE_M_CALLBACK_FLAGS,
226 226 ixgbe_m_stat,
227 227 ixgbe_m_start,
228 228 ixgbe_m_stop,
229 229 ixgbe_m_promisc,
230 230 ixgbe_m_multicst,
231 231 NULL,
232 232 NULL,
233 233 NULL,
234 234 ixgbe_m_ioctl,
235 235 ixgbe_m_getcapab,
236 236 NULL,
237 237 NULL,
238 238 ixgbe_m_setprop,
239 239 ixgbe_m_getprop,
240 240 ixgbe_m_propinfo
241 241 };
242 242
243 243 /*
244 244 * Initialize capabilities of each supported adapter type
245 245 */
246 246 static adapter_info_t ixgbe_82598eb_cap = {
247 247 64, /* maximum number of rx queues */
248 248 1, /* minimum number of rx queues */
249 249 64, /* default number of rx queues */
250 250 16, /* maximum number of rx groups */
251 251 1, /* minimum number of rx groups */
252 252 1, /* default number of rx groups */
253 253 32, /* maximum number of tx queues */
254 254 1, /* minimum number of tx queues */
255 255 8, /* default number of tx queues */
256 256 16366, /* maximum MTU size */
257 257 0xFFFF, /* maximum interrupt throttle rate */
258 258 0, /* minimum interrupt throttle rate */
259 259 200, /* default interrupt throttle rate */
260 260 18, /* maximum total msix vectors */
261 261 16, /* maximum number of ring vectors */
262 262 2, /* maximum number of other vectors */
263 263 IXGBE_EICR_LSC, /* "other" interrupt types handled */
264 264 0, /* "other" interrupt types enable mask */
265 265 (IXGBE_FLAG_DCA_CAPABLE /* capability flags */
266 266 | IXGBE_FLAG_RSS_CAPABLE
267 267 | IXGBE_FLAG_VMDQ_CAPABLE)
268 268 };
269 269
270 270 static adapter_info_t ixgbe_82599eb_cap = {
271 271 128, /* maximum number of rx queues */
272 272 1, /* minimum number of rx queues */
273 273 128, /* default number of rx queues */
274 274 64, /* maximum number of rx groups */
275 275 1, /* minimum number of rx groups */
276 276 1, /* default number of rx groups */
277 277 128, /* maximum number of tx queues */
278 278 1, /* minimum number of tx queues */
279 279 8, /* default number of tx queues */
280 280 15500, /* maximum MTU size */
281 281 0xFF8, /* maximum interrupt throttle rate */
282 282 0, /* minimum interrupt throttle rate */
283 283 200, /* default interrupt throttle rate */
284 284 64, /* maximum total msix vectors */
285 285 16, /* maximum number of ring vectors */
286 286 2, /* maximum number of other vectors */
287 287 (IXGBE_EICR_LSC
288 288 | IXGBE_EICR_GPI_SDP1
289 289 | IXGBE_EICR_GPI_SDP2), /* "other" interrupt types handled */
290 290
291 291 (IXGBE_SDP1_GPIEN
292 292 | IXGBE_SDP2_GPIEN), /* "other" interrupt types enable mask */
293 293
294 294 (IXGBE_FLAG_DCA_CAPABLE
295 295 | IXGBE_FLAG_RSS_CAPABLE
296 296 | IXGBE_FLAG_VMDQ_CAPABLE
297 297 | IXGBE_FLAG_RSC_CAPABLE
298 298 | IXGBE_FLAG_SFP_PLUG_CAPABLE) /* capability flags */
299 299 };
300 300
301 301 static adapter_info_t ixgbe_X540_cap = {
302 302 128, /* maximum number of rx queues */
303 303 1, /* minimum number of rx queues */
304 304 128, /* default number of rx queues */
305 305 64, /* maximum number of rx groups */
306 306 1, /* minimum number of rx groups */
307 307 1, /* default number of rx groups */
308 308 128, /* maximum number of tx queues */
309 309 1, /* minimum number of tx queues */
310 310 8, /* default number of tx queues */
311 311 15500, /* maximum MTU size */
312 312 0xFF8, /* maximum interrupt throttle rate */
313 313 0, /* minimum interrupt throttle rate */
314 314 200, /* default interrupt throttle rate */
315 315 64, /* maximum total msix vectors */
316 316 16, /* maximum number of ring vectors */
317 317 2, /* maximum number of other vectors */
318 318 (IXGBE_EICR_LSC
319 319 | IXGBE_EICR_GPI_SDP1_X540
320 320 | IXGBE_EICR_GPI_SDP2_X540), /* "other" interrupt types handled */
321 321
322 322 (IXGBE_SDP1_GPIEN_X540
323 323 | IXGBE_SDP2_GPIEN_X540), /* "other" interrupt types enable mask */
324 324
325 325 (IXGBE_FLAG_DCA_CAPABLE
326 326 | IXGBE_FLAG_RSS_CAPABLE
327 327 | IXGBE_FLAG_VMDQ_CAPABLE
328 328 | IXGBE_FLAG_RSC_CAPABLE) /* capability flags */
329 329 };
330 330
331 331 static adapter_info_t ixgbe_X550_cap = {
332 332 128, /* maximum number of rx queues */
333 333 1, /* minimum number of rx queues */
334 334 128, /* default number of rx queues */
335 335 64, /* maximum number of rx groups */
336 336 1, /* minimum number of rx groups */
337 337 1, /* default number of rx groups */
338 338 128, /* maximum number of tx queues */
339 339 1, /* minimum number of tx queues */
340 340 8, /* default number of tx queues */
341 341 15500, /* maximum MTU size */
342 342 0xFF8, /* maximum interrupt throttle rate */
343 343 0, /* minimum interrupt throttle rate */
344 344 0x200, /* default interrupt throttle rate */
345 345 64, /* maximum total msix vectors */
346 346 16, /* maximum number of ring vectors */
347 347 2, /* maximum number of other vectors */
348 348 IXGBE_EICR_LSC, /* "other" interrupt types handled */
349 349 0, /* "other" interrupt types enable mask */
350 350 (IXGBE_FLAG_RSS_CAPABLE
351 351 | IXGBE_FLAG_VMDQ_CAPABLE
352 352 | IXGBE_FLAG_RSC_CAPABLE) /* capability flags */
353 353 };
354 354
355 355 /*
356 356 * Module Initialization Functions.
357 357 */
358 358
359 359 int
360 360 _init(void)
361 361 {
362 362 int status;
363 363
364 364 mac_init_ops(&ixgbe_dev_ops, MODULE_NAME);
365 365
366 366 status = mod_install(&ixgbe_modlinkage);
367 367
368 368 if (status != DDI_SUCCESS) {
369 369 mac_fini_ops(&ixgbe_dev_ops);
370 370 }
371 371
372 372 return (status);
373 373 }
374 374
375 375 int
376 376 _fini(void)
377 377 {
378 378 int status;
379 379
380 380 status = mod_remove(&ixgbe_modlinkage);
381 381
382 382 if (status == DDI_SUCCESS) {
383 383 mac_fini_ops(&ixgbe_dev_ops);
384 384 }
385 385
386 386 return (status);
387 387 }
388 388
389 389 int
390 390 _info(struct modinfo *modinfop)
391 391 {
392 392 int status;
393 393
394 394 status = mod_info(&ixgbe_modlinkage, modinfop);
395 395
396 396 return (status);
397 397 }
398 398
399 399 /*
400 400 * ixgbe_attach - Driver attach.
401 401 *
402 402 * This function is the device specific initialization entry
403 403 * point. This entry point is required and must be written.
404 404 * The DDI_ATTACH command must be provided in the attach entry
405 405 * point. When attach() is called with cmd set to DDI_ATTACH,
406 406 * all normal kernel services (such as kmem_alloc(9F)) are
407 407 * available for use by the driver.
408 408 *
409 409 * The attach() function will be called once for each instance
410 410 * of the device on the system with cmd set to DDI_ATTACH.
411 411 * Until attach() succeeds, the only driver entry points which
412 412 * may be called are open(9E) and getinfo(9E).
413 413 */
414 414 static int
415 415 ixgbe_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
416 416 {
417 417 ixgbe_t *ixgbe;
418 418 struct ixgbe_osdep *osdep;
419 419 struct ixgbe_hw *hw;
420 420 int instance;
421 421 char taskqname[32];
422 422
423 423 /*
424 424 * Check the command and perform corresponding operations
425 425 */
426 426 switch (cmd) {
427 427 default:
428 428 return (DDI_FAILURE);
429 429
430 430 case DDI_RESUME:
431 431 return (ixgbe_resume(devinfo));
432 432
433 433 case DDI_ATTACH:
434 434 break;
435 435 }
436 436
437 437 /* Get the device instance */
438 438 instance = ddi_get_instance(devinfo);
439 439
440 440 /* Allocate memory for the instance data structure */
441 441 ixgbe = kmem_zalloc(sizeof (ixgbe_t), KM_SLEEP);
442 442
443 443 ixgbe->dip = devinfo;
444 444 ixgbe->instance = instance;
445 445
446 446 hw = &ixgbe->hw;
447 447 osdep = &ixgbe->osdep;
448 448 hw->back = osdep;
449 449 osdep->ixgbe = ixgbe;
450 450
451 451 /* Attach the instance pointer to the dev_info data structure */
452 452 ddi_set_driver_private(devinfo, ixgbe);
453 453
454 454 /*
455 455 * Initialize for FMA support
456 456 */
457 457 ixgbe->fm_capabilities = ixgbe_get_prop(ixgbe, PROP_FM_CAPABLE,
458 458 0, 0x0f, DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
459 459 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
460 460 ixgbe_fm_init(ixgbe);
461 461 ixgbe->attach_progress |= ATTACH_PROGRESS_FM_INIT;
462 462
463 463 /*
464 464 * Map PCI config space registers
465 465 */
466 466 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
467 467 ixgbe_error(ixgbe, "Failed to map PCI configurations");
468 468 goto attach_fail;
469 469 }
470 470 ixgbe->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
471 471
472 472 /*
473 473 * Identify the chipset family
474 474 */
475 475 if (ixgbe_identify_hardware(ixgbe) != IXGBE_SUCCESS) {
476 476 ixgbe_error(ixgbe, "Failed to identify hardware");
477 477 goto attach_fail;
478 478 }
479 479
480 480 /*
481 481 * Map device registers
482 482 */
483 483 if (ixgbe_regs_map(ixgbe) != IXGBE_SUCCESS) {
484 484 ixgbe_error(ixgbe, "Failed to map device registers");
485 485 goto attach_fail;
486 486 }
487 487 ixgbe->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
488 488
489 489 /*
490 490 * Initialize driver parameters
491 491 */
492 492 ixgbe_init_properties(ixgbe);
493 493 ixgbe->attach_progress |= ATTACH_PROGRESS_PROPS;
494 494
495 495 /*
496 496 * Register interrupt callback
497 497 */
498 498 if (ixgbe_intr_cb_register(ixgbe) != IXGBE_SUCCESS) {
499 499 ixgbe_error(ixgbe, "Failed to register interrupt callback");
500 500 goto attach_fail;
501 501 }
502 502
503 503 /*
504 504 * Allocate interrupts
505 505 */
506 506 if (ixgbe_alloc_intrs(ixgbe) != IXGBE_SUCCESS) {
507 507 ixgbe_error(ixgbe, "Failed to allocate interrupts");
508 508 goto attach_fail;
509 509 }
510 510 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
511 511
512 512 /*
513 513 * Allocate rx/tx rings based on the ring numbers.
514 514 * The actual numbers of rx/tx rings are decided by the number of
515 515 * allocated interrupt vectors, so we should allocate the rings after
516 516 * interrupts are allocated.
517 517 */
518 518 if (ixgbe_alloc_rings(ixgbe) != IXGBE_SUCCESS) {
519 519 ixgbe_error(ixgbe, "Failed to allocate rx and tx rings");
520 520 goto attach_fail;
521 521 }
522 522 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
523 523
524 524 /*
525 525 * Map rings to interrupt vectors
526 526 */
527 527 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
528 528 ixgbe_error(ixgbe, "Failed to map interrupts to vectors");
529 529 goto attach_fail;
530 530 }
531 531
532 532 /*
533 533 * Add interrupt handlers
534 534 */
535 535 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
536 536 ixgbe_error(ixgbe, "Failed to add interrupt handlers");
537 537 goto attach_fail;
538 538 }
539 539 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
540 540
541 541 /*
542 542 * Create a taskq for sfp-change
543 543 */
544 544 (void) sprintf(taskqname, "ixgbe%d_sfp_taskq", instance);
545 545 if ((ixgbe->sfp_taskq = ddi_taskq_create(devinfo, taskqname,
546 546 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
547 547 ixgbe_error(ixgbe, "sfp_taskq create failed");
548 548 goto attach_fail;
549 549 }
550 550 ixgbe->attach_progress |= ATTACH_PROGRESS_SFP_TASKQ;
551 551
552 552 /*
553 553 * Create a taskq for over-temp
554 554 */
555 555 (void) sprintf(taskqname, "ixgbe%d_overtemp_taskq", instance);
556 556 if ((ixgbe->overtemp_taskq = ddi_taskq_create(devinfo, taskqname,
557 557 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
558 558 ixgbe_error(ixgbe, "overtemp_taskq create failed");
559 559 goto attach_fail;
560 560 }
561 561 ixgbe->attach_progress |= ATTACH_PROGRESS_OVERTEMP_TASKQ;
562 562
563 563 /*
564 564 * Create a taskq for processing external PHY interrupts
565 565 */
566 566 (void) sprintf(taskqname, "ixgbe%d_phy_taskq", instance);
567 567 if ((ixgbe->phy_taskq = ddi_taskq_create(devinfo, taskqname,
568 568 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
569 569 ixgbe_error(ixgbe, "phy_taskq create failed");
570 570 goto attach_fail;
571 571 }
572 572 ixgbe->attach_progress |= ATTACH_PROGRESS_PHY_TASKQ;
573 573
574 574 /*
575 575 * Initialize driver parameters
576 576 */
577 577 if (ixgbe_init_driver_settings(ixgbe) != IXGBE_SUCCESS) {
578 578 ixgbe_error(ixgbe, "Failed to initialize driver settings");
579 579 goto attach_fail;
580 580 }
581 581
582 582 /*
583 583 * Initialize mutexes for this device.
584 584 * Do this before enabling the interrupt handler and
585 585 * register the softint to avoid the condition where
586 586 * interrupt handler can try using uninitialized mutex.
587 587 */
588 588 ixgbe_init_locks(ixgbe);
589 589 ixgbe->attach_progress |= ATTACH_PROGRESS_LOCKS;
590 590
591 591 /*
592 592 * Initialize chipset hardware
593 593 */
594 594 if (ixgbe_init(ixgbe) != IXGBE_SUCCESS) {
595 595 ixgbe_error(ixgbe, "Failed to initialize adapter");
596 596 goto attach_fail;
597 597 }
598 598 ixgbe->link_check_complete = B_FALSE;
599 599 ixgbe->link_check_hrtime = gethrtime() +
600 600 (IXGBE_LINK_UP_TIME * 100000000ULL);
601 601 ixgbe->attach_progress |= ATTACH_PROGRESS_INIT;
602 602
603 603 if (ixgbe_check_acc_handle(ixgbe->osdep.cfg_handle) != DDI_FM_OK) {
604 604 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
605 605 goto attach_fail;
606 606 }
607 607
608 608 /*
609 609 * Initialize adapter capabilities
610 610 */
611 611 ixgbe_init_params(ixgbe);
612 612
613 613 /*
614 614 * Initialize statistics
615 615 */
616 616 if (ixgbe_init_stats(ixgbe) != IXGBE_SUCCESS) {
617 617 ixgbe_error(ixgbe, "Failed to initialize statistics");
618 618 goto attach_fail;
619 619 }
620 620 ixgbe->attach_progress |= ATTACH_PROGRESS_STATS;
621 621
622 622 /*
623 623 * Register the driver to the MAC
624 624 */
625 625 if (ixgbe_register_mac(ixgbe) != IXGBE_SUCCESS) {
626 626 ixgbe_error(ixgbe, "Failed to register MAC");
627 627 goto attach_fail;
628 628 }
629 629 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
630 630 ixgbe->attach_progress |= ATTACH_PROGRESS_MAC;
631 631
632 632 ixgbe->periodic_id = ddi_periodic_add(ixgbe_link_timer, ixgbe,
633 633 IXGBE_CYCLIC_PERIOD, DDI_IPL_0);
634 634 if (ixgbe->periodic_id == 0) {
635 635 ixgbe_error(ixgbe, "Failed to add the link check timer");
636 636 goto attach_fail;
637 637 }
638 638 ixgbe->attach_progress |= ATTACH_PROGRESS_LINK_TIMER;
639 639
640 640 /*
641 641 * Now that mutex locks are initialized, and the chip is also
642 642 * initialized, enable interrupts.
643 643 */
644 644 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
645 645 ixgbe_error(ixgbe, "Failed to enable DDI interrupts");
646 646 goto attach_fail;
647 647 }
648 648 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
649 649
650 650 ixgbe_log(ixgbe, "%s", ixgbe_ident);
651 651 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_INITIALIZED);
652 652
653 653 return (DDI_SUCCESS);
654 654
655 655 attach_fail:
656 656 ixgbe_unconfigure(devinfo, ixgbe);
657 657 return (DDI_FAILURE);
658 658 }
659 659
660 660 /*
661 661 * ixgbe_detach - Driver detach.
662 662 *
663 663 * The detach() function is the complement of the attach routine.
664 664 * If cmd is set to DDI_DETACH, detach() is used to remove the
665 665 * state associated with a given instance of a device node
666 666 * prior to the removal of that instance from the system.
667 667 *
668 668 * The detach() function will be called once for each instance
669 669 * of the device for which there has been a successful attach()
670 670 * once there are no longer any opens on the device.
671 671 *
672 672 * Interrupts routine are disabled, All memory allocated by this
673 673 * driver are freed.
674 674 */
675 675 static int
676 676 ixgbe_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
677 677 {
678 678 ixgbe_t *ixgbe;
679 679
680 680 /*
681 681 * Check detach command
682 682 */
683 683 switch (cmd) {
684 684 default:
685 685 return (DDI_FAILURE);
686 686
687 687 case DDI_SUSPEND:
688 688 return (ixgbe_suspend(devinfo));
689 689
690 690 case DDI_DETACH:
691 691 break;
692 692 }
693 693
694 694 /*
695 695 * Get the pointer to the driver private data structure
696 696 */
697 697 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
698 698 if (ixgbe == NULL)
699 699 return (DDI_FAILURE);
700 700
701 701 /*
702 702 * If the device is still running, it needs to be stopped first.
703 703 * This check is necessary because under some specific circumstances,
704 704 * the detach routine can be called without stopping the interface
705 705 * first.
706 706 */
707 707 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
708 708 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
709 709 mutex_enter(&ixgbe->gen_lock);
710 710 ixgbe_stop(ixgbe, B_TRUE);
711 711 mutex_exit(&ixgbe->gen_lock);
712 712 /* Disable and stop the watchdog timer */
713 713 ixgbe_disable_watchdog_timer(ixgbe);
714 714 }
715 715
716 716 /*
717 717 * Check if there are still rx buffers held by the upper layer.
718 718 * If so, fail the detach.
719 719 */
720 720 if (!ixgbe_rx_drain(ixgbe))
721 721 return (DDI_FAILURE);
722 722
723 723 /*
724 724 * Do the remaining unconfigure routines
725 725 */
726 726 ixgbe_unconfigure(devinfo, ixgbe);
727 727
728 728 return (DDI_SUCCESS);
729 729 }
730 730
731 731 /*
732 732 * quiesce(9E) entry point.
733 733 *
734 734 * This function is called when the system is single-threaded at high
735 735 * PIL with preemption disabled. Therefore, this function must not be
736 736 * blocked.
737 737 *
738 738 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
739 739 * DDI_FAILURE indicates an error condition and should almost never happen.
740 740 */
741 741 static int
742 742 ixgbe_quiesce(dev_info_t *devinfo)
743 743 {
744 744 ixgbe_t *ixgbe;
745 745 struct ixgbe_hw *hw;
746 746
747 747 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
748 748
749 749 if (ixgbe == NULL)
750 750 return (DDI_FAILURE);
751 751
752 752 hw = &ixgbe->hw;
753 753
754 754 /*
755 755 * Disable the adapter interrupts
756 756 */
757 757 ixgbe_disable_adapter_interrupts(ixgbe);
758 758
759 759 /*
760 760 * Tell firmware driver is no longer in control
761 761 */
762 762 ixgbe_release_driver_control(hw);
763 763
764 764 /*
765 765 * Reset the chipset
766 766 */
767 767 (void) ixgbe_reset_hw(hw);
768 768
769 769 /*
770 770 * Reset PHY
771 771 */
772 772 (void) ixgbe_reset_phy(hw);
773 773
774 774 return (DDI_SUCCESS);
775 775 }
776 776
777 777 static void
778 778 ixgbe_unconfigure(dev_info_t *devinfo, ixgbe_t *ixgbe)
779 779 {
780 780 /*
781 781 * Disable interrupt
782 782 */
783 783 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
784 784 (void) ixgbe_disable_intrs(ixgbe);
785 785 }
786 786
787 787 /*
788 788 * remove the link check timer
789 789 */
790 790 if (ixgbe->attach_progress & ATTACH_PROGRESS_LINK_TIMER) {
791 791 if (ixgbe->periodic_id != NULL) {
792 792 ddi_periodic_delete(ixgbe->periodic_id);
793 793 ixgbe->periodic_id = NULL;
794 794 }
795 795 }
796 796
797 797 /*
798 798 * Unregister MAC
799 799 */
800 800 if (ixgbe->attach_progress & ATTACH_PROGRESS_MAC) {
801 801 (void) mac_unregister(ixgbe->mac_hdl);
802 802 }
803 803
804 804 /*
805 805 * Free statistics
806 806 */
807 807 if (ixgbe->attach_progress & ATTACH_PROGRESS_STATS) {
808 808 kstat_delete((kstat_t *)ixgbe->ixgbe_ks);
809 809 }
810 810
811 811 /*
812 812 * Remove interrupt handlers
813 813 */
814 814 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
815 815 ixgbe_rem_intr_handlers(ixgbe);
816 816 }
817 817
818 818 /*
819 819 * Remove taskq for sfp-status-change
820 820 */
821 821 if (ixgbe->attach_progress & ATTACH_PROGRESS_SFP_TASKQ) {
822 822 ddi_taskq_destroy(ixgbe->sfp_taskq);
823 823 }
824 824
825 825 /*
826 826 * Remove taskq for over-temp
827 827 */
828 828 if (ixgbe->attach_progress & ATTACH_PROGRESS_OVERTEMP_TASKQ) {
829 829 ddi_taskq_destroy(ixgbe->overtemp_taskq);
830 830 }
831 831
832 832 /*
833 833 * Remove taskq for external PHYs
834 834 */
835 835 if (ixgbe->attach_progress & ATTACH_PROGRESS_PHY_TASKQ) {
836 836 ddi_taskq_destroy(ixgbe->phy_taskq);
837 837 }
838 838
839 839 /*
840 840 * Remove interrupts
841 841 */
842 842 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
843 843 ixgbe_rem_intrs(ixgbe);
844 844 }
845 845
846 846 /*
847 847 * Unregister interrupt callback handler
848 848 */
849 849 if (ixgbe->cb_hdl != NULL) {
850 850 (void) ddi_cb_unregister(ixgbe->cb_hdl);
851 851 }
852 852
853 853 /*
854 854 * Remove driver properties
855 855 */
856 856 if (ixgbe->attach_progress & ATTACH_PROGRESS_PROPS) {
857 857 (void) ddi_prop_remove_all(devinfo);
858 858 }
859 859
860 860 /*
861 861 * Stop the chipset
862 862 */
863 863 if (ixgbe->attach_progress & ATTACH_PROGRESS_INIT) {
864 864 mutex_enter(&ixgbe->gen_lock);
865 865 ixgbe_chip_stop(ixgbe);
866 866 mutex_exit(&ixgbe->gen_lock);
867 867 }
868 868
869 869 /*
870 870 * Free register handle
871 871 */
872 872 if (ixgbe->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
873 873 if (ixgbe->osdep.reg_handle != NULL)
874 874 ddi_regs_map_free(&ixgbe->osdep.reg_handle);
875 875 }
876 876
877 877 /*
878 878 * Free PCI config handle
879 879 */
880 880 if (ixgbe->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
881 881 if (ixgbe->osdep.cfg_handle != NULL)
882 882 pci_config_teardown(&ixgbe->osdep.cfg_handle);
883 883 }
884 884
885 885 /*
886 886 * Free locks
887 887 */
888 888 if (ixgbe->attach_progress & ATTACH_PROGRESS_LOCKS) {
889 889 ixgbe_destroy_locks(ixgbe);
890 890 }
891 891
892 892 /*
893 893 * Free the rx/tx rings
894 894 */
895 895 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
896 896 ixgbe_free_rings(ixgbe);
897 897 }
898 898
899 899 /*
900 900 * Unregister FMA capabilities
901 901 */
902 902 if (ixgbe->attach_progress & ATTACH_PROGRESS_FM_INIT) {
903 903 ixgbe_fm_fini(ixgbe);
904 904 }
905 905
906 906 /*
907 907 * Free the driver data structure
908 908 */
909 909 kmem_free(ixgbe, sizeof (ixgbe_t));
910 910
911 911 ddi_set_driver_private(devinfo, NULL);
912 912 }
913 913
914 914 /*
915 915 * ixgbe_register_mac - Register the driver and its function pointers with
916 916 * the GLD interface.
917 917 */
918 918 static int
919 919 ixgbe_register_mac(ixgbe_t *ixgbe)
920 920 {
921 921 struct ixgbe_hw *hw = &ixgbe->hw;
922 922 mac_register_t *mac;
923 923 int status;
924 924
925 925 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
926 926 return (IXGBE_FAILURE);
927 927
928 928 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
929 929 mac->m_driver = ixgbe;
930 930 mac->m_dip = ixgbe->dip;
931 931 mac->m_src_addr = hw->mac.addr;
932 932 mac->m_callbacks = &ixgbe_m_callbacks;
933 933 mac->m_min_sdu = 0;
934 934 mac->m_max_sdu = ixgbe->default_mtu;
935 935 mac->m_margin = VLAN_TAGSZ;
936 936 mac->m_priv_props = ixgbe_priv_props;
937 937 mac->m_v12n = MAC_VIRT_LEVEL1;
938 938
939 939 status = mac_register(mac, &ixgbe->mac_hdl);
940 940
941 941 mac_free(mac);
942 942
943 943 return ((status == 0) ? IXGBE_SUCCESS : IXGBE_FAILURE);
944 944 }
945 945
946 946 /*
947 947 * ixgbe_identify_hardware - Identify the type of the chipset.
948 948 */
949 949 static int
950 950 ixgbe_identify_hardware(ixgbe_t *ixgbe)
951 951 {
952 952 struct ixgbe_hw *hw = &ixgbe->hw;
953 953 struct ixgbe_osdep *osdep = &ixgbe->osdep;
954 954
955 955 /*
956 956 * Get the device id
957 957 */
958 958 hw->vendor_id =
959 959 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
960 960 hw->device_id =
961 961 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
962 962 hw->revision_id =
963 963 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
964 964 hw->subsystem_device_id =
965 965 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
966 966 hw->subsystem_vendor_id =
967 967 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
968 968
969 969 /*
970 970 * Set the mac type of the adapter based on the device id
971 971 */
972 972 if (ixgbe_set_mac_type(hw) != IXGBE_SUCCESS) {
973 973 return (IXGBE_FAILURE);
974 974 }
975 975
976 976 /*
977 977 * Install adapter capabilities
978 978 */
979 979 switch (hw->mac.type) {
980 980 case ixgbe_mac_82598EB:
981 981 IXGBE_DEBUGLOG_0(ixgbe, "identify 82598 adapter\n");
982 982 ixgbe->capab = &ixgbe_82598eb_cap;
983 983
984 984 if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
985 985 ixgbe->capab->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
986 986 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP1;
987 987 ixgbe->capab->other_gpie |= IXGBE_SDP1_GPIEN;
988 988 }
989 989 break;
990 990
991 991 case ixgbe_mac_82599EB:
992 992 IXGBE_DEBUGLOG_0(ixgbe, "identify 82599 adapter\n");
993 993 ixgbe->capab = &ixgbe_82599eb_cap;
994 994
995 995 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) {
996 996 ixgbe->capab->flags |= IXGBE_FLAG_TEMP_SENSOR_CAPABLE;
997 997 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP0;
998 998 ixgbe->capab->other_gpie |= IXGBE_SDP0_GPIEN;
999 999 }
1000 1000 break;
1001 1001
1002 1002 case ixgbe_mac_X540:
1003 1003 IXGBE_DEBUGLOG_0(ixgbe, "identify X540 adapter\n");
1004 1004 ixgbe->capab = &ixgbe_X540_cap;
1005 1005 /*
1006 1006 * For now, X540 is all set in its capab structure.
1007 1007 * As other X540 variants show up, things can change here.
1008 1008 */
1009 1009 break;
1010 1010
1011 1011 case ixgbe_mac_X550:
1012 1012 case ixgbe_mac_X550EM_x:
1013 1013 case ixgbe_mac_X550EM_a:
1014 1014 IXGBE_DEBUGLOG_0(ixgbe, "identify X550 adapter\n");
1015 1015 ixgbe->capab = &ixgbe_X550_cap;
1016 1016
1017 1017 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
1018 1018 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
1019 1019 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N ||
1020 1020 hw->device_id == IXGBE_DEV_ID_X550EM_A_QSFP ||
1021 1021 hw->device_id == IXGBE_DEV_ID_X550EM_A_QSFP_N) {
1022 1022 ixgbe->capab->flags |= IXGBE_FLAG_SFP_PLUG_CAPABLE;
1023 1023 }
1024 1024
1025 1025 /*
1026 1026 * Link detection on X552 SFP+ and X552/X557-AT
1027 1027 */
1028 1028 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
1029 1029 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
1030 1030 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N ||
1031 1031 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1032 1032 ixgbe->capab->other_intr |=
1033 1033 IXGBE_EIMS_GPI_SDP0_BY_MAC(hw);
1034 1034 }
1035 1035 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1036 1036 ixgbe->capab->other_gpie |= IXGBE_SDP0_GPIEN_X540;
1037 1037 }
1038 1038 break;
1039 1039
1040 1040 default:
1041 1041 IXGBE_DEBUGLOG_1(ixgbe,
1042 1042 "adapter not supported in ixgbe_identify_hardware(): %d\n",
1043 1043 hw->mac.type);
1044 1044 return (IXGBE_FAILURE);
1045 1045 }
1046 1046
1047 1047 return (IXGBE_SUCCESS);
1048 1048 }
1049 1049
1050 1050 /*
1051 1051 * ixgbe_regs_map - Map the device registers.
1052 1052 *
1053 1053 */
1054 1054 static int
1055 1055 ixgbe_regs_map(ixgbe_t *ixgbe)
1056 1056 {
1057 1057 dev_info_t *devinfo = ixgbe->dip;
1058 1058 struct ixgbe_hw *hw = &ixgbe->hw;
1059 1059 struct ixgbe_osdep *osdep = &ixgbe->osdep;
1060 1060 off_t mem_size;
1061 1061
1062 1062 /*
1063 1063 * First get the size of device registers to be mapped.
1064 1064 */
1065 1065 if (ddi_dev_regsize(devinfo, IXGBE_ADAPTER_REGSET, &mem_size)
1066 1066 != DDI_SUCCESS) {
1067 1067 return (IXGBE_FAILURE);
1068 1068 }
1069 1069
1070 1070 /*
1071 1071 * Call ddi_regs_map_setup() to map registers
1072 1072 */
1073 1073 if ((ddi_regs_map_setup(devinfo, IXGBE_ADAPTER_REGSET,
1074 1074 (caddr_t *)&hw->hw_addr, 0,
1075 1075 mem_size, &ixgbe_regs_acc_attr,
1076 1076 &osdep->reg_handle)) != DDI_SUCCESS) {
1077 1077 return (IXGBE_FAILURE);
1078 1078 }
1079 1079
1080 1080 return (IXGBE_SUCCESS);
1081 1081 }
1082 1082
1083 1083 /*
1084 1084 * ixgbe_init_properties - Initialize driver properties.
1085 1085 */
1086 1086 static void
1087 1087 ixgbe_init_properties(ixgbe_t *ixgbe)
1088 1088 {
1089 1089 /*
1090 1090 * Get conf file properties, including link settings
1091 1091 * jumbo frames, ring number, descriptor number, etc.
1092 1092 */
1093 1093 ixgbe_get_conf(ixgbe);
1094 1094 }
1095 1095
1096 1096 /*
1097 1097 * ixgbe_init_driver_settings - Initialize driver settings.
1098 1098 *
1099 1099 * The settings include hardware function pointers, bus information,
1100 1100 * rx/tx rings settings, link state, and any other parameters that
1101 1101 * need to be setup during driver initialization.
1102 1102 */
1103 1103 static int
1104 1104 ixgbe_init_driver_settings(ixgbe_t *ixgbe)
1105 1105 {
1106 1106 struct ixgbe_hw *hw = &ixgbe->hw;
1107 1107 dev_info_t *devinfo = ixgbe->dip;
1108 1108 ixgbe_rx_ring_t *rx_ring;
1109 1109 ixgbe_rx_group_t *rx_group;
1110 1110 ixgbe_tx_ring_t *tx_ring;
1111 1111 uint32_t rx_size;
1112 1112 uint32_t tx_size;
1113 1113 uint32_t ring_per_group;
1114 1114 int i;
1115 1115
1116 1116 /*
1117 1117 * Initialize chipset specific hardware function pointers
1118 1118 */
1119 1119 if (ixgbe_init_shared_code(hw) != IXGBE_SUCCESS) {
1120 1120 return (IXGBE_FAILURE);
1121 1121 }
1122 1122
1123 1123 /*
1124 1124 * Get the system page size
1125 1125 */
1126 1126 ixgbe->sys_page_size = ddi_ptob(devinfo, (ulong_t)1);
1127 1127
1128 1128 /*
1129 1129 * Set rx buffer size
1130 1130 *
1131 1131 * The IP header alignment room is counted in the calculation.
1132 1132 * The rx buffer size is in unit of 1K that is required by the
1133 1133 * chipset hardware.
1134 1134 */
1135 1135 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM;
1136 1136 ixgbe->rx_buf_size = ((rx_size >> 10) +
1137 1137 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1138 1138
1139 1139 /*
1140 1140 * Set tx buffer size
1141 1141 */
1142 1142 tx_size = ixgbe->max_frame_size;
1143 1143 ixgbe->tx_buf_size = ((tx_size >> 10) +
1144 1144 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
1145 1145
1146 1146 /*
1147 1147 * Initialize rx/tx rings/groups parameters
1148 1148 */
1149 1149 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
1150 1150 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1151 1151 rx_ring = &ixgbe->rx_rings[i];
1152 1152 rx_ring->index = i;
1153 1153 rx_ring->ixgbe = ixgbe;
1154 1154 rx_ring->group_index = i / ring_per_group;
1155 1155 rx_ring->hw_index = ixgbe_get_hw_rx_index(ixgbe, i);
1156 1156 }
1157 1157
1158 1158 for (i = 0; i < ixgbe->num_rx_groups; i++) {
1159 1159 rx_group = &ixgbe->rx_groups[i];
1160 1160 rx_group->index = i;
1161 1161 rx_group->ixgbe = ixgbe;
1162 1162 }
1163 1163
1164 1164 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1165 1165 tx_ring = &ixgbe->tx_rings[i];
1166 1166 tx_ring->index = i;
1167 1167 tx_ring->ixgbe = ixgbe;
1168 1168 if (ixgbe->tx_head_wb_enable)
1169 1169 tx_ring->tx_recycle = ixgbe_tx_recycle_head_wb;
1170 1170 else
1171 1171 tx_ring->tx_recycle = ixgbe_tx_recycle_legacy;
1172 1172
1173 1173 tx_ring->ring_size = ixgbe->tx_ring_size;
1174 1174 tx_ring->free_list_size = ixgbe->tx_ring_size +
1175 1175 (ixgbe->tx_ring_size >> 1);
1176 1176 }
1177 1177
1178 1178 /*
1179 1179 * Initialize values of interrupt throttling rate
1180 1180 */
1181 1181 for (i = 1; i < MAX_INTR_VECTOR; i++)
1182 1182 ixgbe->intr_throttling[i] = ixgbe->intr_throttling[0];
1183 1183
1184 1184 /*
1185 1185 * The initial link state should be "unknown"
1186 1186 */
1187 1187 ixgbe->link_state = LINK_STATE_UNKNOWN;
1188 1188
1189 1189 return (IXGBE_SUCCESS);
1190 1190 }
1191 1191
1192 1192 /*
1193 1193 * ixgbe_init_locks - Initialize locks.
1194 1194 */
1195 1195 static void
1196 1196 ixgbe_init_locks(ixgbe_t *ixgbe)
1197 1197 {
1198 1198 ixgbe_rx_ring_t *rx_ring;
1199 1199 ixgbe_tx_ring_t *tx_ring;
1200 1200 int i;
1201 1201
1202 1202 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1203 1203 rx_ring = &ixgbe->rx_rings[i];
1204 1204 mutex_init(&rx_ring->rx_lock, NULL,
1205 1205 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1206 1206 }
1207 1207
1208 1208 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1209 1209 tx_ring = &ixgbe->tx_rings[i];
1210 1210 mutex_init(&tx_ring->tx_lock, NULL,
1211 1211 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1212 1212 mutex_init(&tx_ring->recycle_lock, NULL,
1213 1213 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1214 1214 mutex_init(&tx_ring->tcb_head_lock, NULL,
1215 1215 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1216 1216 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1217 1217 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1218 1218 }
1219 1219
1220 1220 mutex_init(&ixgbe->gen_lock, NULL,
1221 1221 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1222 1222
1223 1223 mutex_init(&ixgbe->watchdog_lock, NULL,
1224 1224 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1225 1225 }
1226 1226
1227 1227 /*
1228 1228 * ixgbe_destroy_locks - Destroy locks.
1229 1229 */
1230 1230 static void
1231 1231 ixgbe_destroy_locks(ixgbe_t *ixgbe)
1232 1232 {
1233 1233 ixgbe_rx_ring_t *rx_ring;
1234 1234 ixgbe_tx_ring_t *tx_ring;
1235 1235 int i;
1236 1236
1237 1237 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1238 1238 rx_ring = &ixgbe->rx_rings[i];
1239 1239 mutex_destroy(&rx_ring->rx_lock);
1240 1240 }
1241 1241
1242 1242 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1243 1243 tx_ring = &ixgbe->tx_rings[i];
1244 1244 mutex_destroy(&tx_ring->tx_lock);
1245 1245 mutex_destroy(&tx_ring->recycle_lock);
1246 1246 mutex_destroy(&tx_ring->tcb_head_lock);
1247 1247 mutex_destroy(&tx_ring->tcb_tail_lock);
1248 1248 }
1249 1249
1250 1250 mutex_destroy(&ixgbe->gen_lock);
1251 1251 mutex_destroy(&ixgbe->watchdog_lock);
1252 1252 }
1253 1253
1254 1254 /*
1255 1255 * We need to try and determine which LED index in hardware corresponds to the
1256 1256 * link/activity LED. This is the one that'll be overwritten when we perform
1257 1257 * GLDv3 LED activity.
1258 1258 */
1259 1259 static void
1260 1260 ixgbe_led_init(ixgbe_t *ixgbe)
1261 1261 {
1262 1262 uint32_t reg, i;
1263 1263 struct ixgbe_hw *hw = &ixgbe->hw;
1264 1264
1265 1265 reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1266 1266 for (i = 0; i < 4; i++) {
1267 1267 if (((reg >> IXGBE_LED_MODE_SHIFT(i)) &
1268 1268 IXGBE_LED_MODE_MASK_BASE) == IXGBE_LED_LINK_ACTIVE) {
1269 1269 ixgbe->ixgbe_led_index = i;
1270 1270 return;
1271 1271 }
1272 1272 }
1273 1273
1274 1274 /*
1275 1275 * If we couldn't determine this, we use the default for various MACs
1276 1276 * based on information Intel has inserted into other drivers over the
1277 1277 * years.
1278 1278 */
1279 1279 switch (hw->mac.type) {
1280 1280 case ixgbe_mac_X550EM_a:
1281 1281 ixgbe->ixgbe_led_index = 0;
1282 1282 break;
1283 1283 case ixgbe_mac_X550EM_x:
1284 1284 ixgbe->ixgbe_led_index = 1;
1285 1285 break;
1286 1286 default:
1287 1287 ixgbe->ixgbe_led_index = 2;
1288 1288 break;
1289 1289 }
1290 1290 }
1291 1291
1292 1292 static int
1293 1293 ixgbe_resume(dev_info_t *devinfo)
1294 1294 {
1295 1295 ixgbe_t *ixgbe;
1296 1296 int i;
1297 1297
1298 1298 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1299 1299 if (ixgbe == NULL)
1300 1300 return (DDI_FAILURE);
1301 1301
1302 1302 mutex_enter(&ixgbe->gen_lock);
1303 1303
1304 1304 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1305 1305 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1306 1306 mutex_exit(&ixgbe->gen_lock);
1307 1307 return (DDI_FAILURE);
1308 1308 }
1309 1309
1310 1310 /*
1311 1311 * Enable and start the watchdog timer
1312 1312 */
1313 1313 ixgbe_enable_watchdog_timer(ixgbe);
1314 1314 }
1315 1315
1316 1316 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_SUSPENDED);
1317 1317
1318 1318 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1319 1319 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1320 1320 mac_tx_ring_update(ixgbe->mac_hdl,
1321 1321 ixgbe->tx_rings[i].ring_handle);
1322 1322 }
1323 1323 }
1324 1324
1325 1325 mutex_exit(&ixgbe->gen_lock);
1326 1326
1327 1327 return (DDI_SUCCESS);
1328 1328 }
1329 1329
1330 1330 static int
1331 1331 ixgbe_suspend(dev_info_t *devinfo)
1332 1332 {
1333 1333 ixgbe_t *ixgbe;
1334 1334
1335 1335 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1336 1336 if (ixgbe == NULL)
1337 1337 return (DDI_FAILURE);
1338 1338
1339 1339 mutex_enter(&ixgbe->gen_lock);
1340 1340
1341 1341 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_SUSPENDED);
1342 1342 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
1343 1343 mutex_exit(&ixgbe->gen_lock);
1344 1344 return (DDI_SUCCESS);
1345 1345 }
1346 1346 ixgbe_stop(ixgbe, B_FALSE);
1347 1347
1348 1348 mutex_exit(&ixgbe->gen_lock);
1349 1349
1350 1350 /*
1351 1351 * Disable and stop the watchdog timer
1352 1352 */
1353 1353 ixgbe_disable_watchdog_timer(ixgbe);
1354 1354
1355 1355 return (DDI_SUCCESS);
1356 1356 }
1357 1357
1358 1358 /*
1359 1359 * ixgbe_init - Initialize the device.
1360 1360 */
1361 1361 static int
1362 1362 ixgbe_init(ixgbe_t *ixgbe)
1363 1363 {
1364 1364 struct ixgbe_hw *hw = &ixgbe->hw;
1365 1365 u8 pbanum[IXGBE_PBANUM_LENGTH];
1366 1366 int rv;
1367 1367
1368 1368 mutex_enter(&ixgbe->gen_lock);
1369 1369
1370 1370 /*
1371 1371 * Configure/Initialize hardware
1372 1372 */
1373 1373 rv = ixgbe_init_hw(hw);
1374 1374 if (rv != IXGBE_SUCCESS) {
1375 1375 switch (rv) {
1376 1376
1377 1377 /*
1378 1378 * The first three errors are not prohibitive to us progressing
1379 1379 * further, and are maily advisory in nature. In the case of a
1380 1380 * SFP module not being present or not deemed supported by the
1381 1381 * common code, we adivse the operator of this fact but carry on
1382 1382 * instead of failing hard, as SFPs can be inserted or replaced
1383 1383 * while the driver is running. In the case of a unknown error,
1384 1384 * we fail-hard, logging the reason and emitting a FMA event.
1385 1385 */
1386 1386 case IXGBE_ERR_EEPROM_VERSION:
1387 1387 ixgbe_error(ixgbe,
1388 1388 "This Intel 10Gb Ethernet device is pre-release and"
1389 1389 " contains outdated firmware. Please contact your"
1390 1390 " hardware vendor for a replacement.");
1391 1391 break;
1392 1392 case IXGBE_ERR_SFP_NOT_PRESENT:
1393 1393 ixgbe_error(ixgbe,
1394 1394 "No SFP+ module detected on this interface. Please "
1395 1395 "install a supported SFP+ module for this "
1396 1396 "interface to become operational.");
1397 1397 break;
1398 1398 case IXGBE_ERR_SFP_NOT_SUPPORTED:
1399 1399 ixgbe_error(ixgbe,
1400 1400 "Unsupported SFP+ module detected. Please replace "
1401 1401 "it with a supported SFP+ module per Intel "
1402 1402 "documentation, or bypass this check with "
1403 1403 "allow_unsupported_sfp=1 in ixgbe.conf.");
1404 1404 break;
1405 1405 default:
1406 1406 ixgbe_error(ixgbe,
1407 1407 "Failed to initialize hardware. ixgbe_init_hw "
1408 1408 "returned %d", rv);
1409 1409 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1410 1410 goto init_fail;
1411 1411 }
1412 1412 }
1413 1413
1414 1414 /*
1415 1415 * Need to init eeprom before validating the checksum.
1416 1416 */
1417 1417 if (ixgbe_init_eeprom_params(hw) < 0) {
1418 1418 ixgbe_error(ixgbe,
1419 1419 "Unable to intitialize the eeprom interface.");
1420 1420 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1421 1421 goto init_fail;
1422 1422 }
1423 1423
1424 1424 /*
1425 1425 * NVM validation
1426 1426 */
1427 1427 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
1428 1428 /*
1429 1429 * Some PCI-E parts fail the first check due to
1430 1430 * the link being in sleep state. Call it again,
1431 1431 * if it fails a second time it's a real issue.
1432 1432 */
1433 1433 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
1434 1434 ixgbe_error(ixgbe,
1435 1435 "Invalid NVM checksum. Please contact "
1436 1436 "the vendor to update the NVM.");
1437 1437 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1438 1438 goto init_fail;
1439 1439 }
1440 1440 }
1441 1441
1442 1442 /*
1443 1443 * Setup default flow control thresholds - enable/disable
1444 1444 * & flow control type is controlled by ixgbe.conf
1445 1445 */
1446 1446 hw->fc.high_water[0] = DEFAULT_FCRTH;
1447 1447 hw->fc.low_water[0] = DEFAULT_FCRTL;
1448 1448 hw->fc.pause_time = DEFAULT_FCPAUSE;
1449 1449 hw->fc.send_xon = B_TRUE;
1450 1450
1451 1451 /*
1452 1452 * Initialize flow control
1453 1453 */
1454 1454 (void) ixgbe_start_hw(hw);
1455 1455
1456 1456 /*
1457 1457 * Initialize link settings
1458 1458 */
1459 1459 (void) ixgbe_driver_setup_link(ixgbe, B_FALSE);
1460 1460
1461 1461 /*
1462 1462 * Initialize the chipset hardware
1463 1463 */
1464 1464 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1465 1465 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1466 1466 goto init_fail;
1467 1467 }
1468 1468
1469 1469 /*
1470 1470 * Read identifying information and place in devinfo.
1471 1471 */
1472 1472 pbanum[0] = '\0';
1473 1473 (void) ixgbe_read_pba_string(hw, pbanum, sizeof (pbanum));
1474 1474 if (*pbanum != '\0') {
1475 1475 (void) ddi_prop_update_string(DDI_DEV_T_NONE, ixgbe->dip,
1476 1476 "printed-board-assembly", (char *)pbanum);
1477 1477 }
1478 1478
1479 1479 /*
1480 1480 * Determine LED index.
1481 1481 */
1482 1482 ixgbe_led_init(ixgbe);
1483 1483
1484 1484 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1485 1485 goto init_fail;
1486 1486 }
1487 1487
1488 1488 mutex_exit(&ixgbe->gen_lock);
1489 1489 return (IXGBE_SUCCESS);
1490 1490
1491 1491 init_fail:
1492 1492 /*
1493 1493 * Reset PHY
1494 1494 */
1495 1495 (void) ixgbe_reset_phy(hw);
1496 1496
1497 1497 mutex_exit(&ixgbe->gen_lock);
1498 1498 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1499 1499 return (IXGBE_FAILURE);
1500 1500 }
1501 1501
1502 1502 /*
1503 1503 * ixgbe_chip_start - Initialize and start the chipset hardware.
1504 1504 */
1505 1505 static int
1506 1506 ixgbe_chip_start(ixgbe_t *ixgbe)
1507 1507 {
1508 1508 struct ixgbe_hw *hw = &ixgbe->hw;
1509 1509 int i;
1510 1510
1511 1511 ASSERT(mutex_owned(&ixgbe->gen_lock));
1512 1512
1513 1513 /*
1514 1514 * Get the mac address
1515 1515 * This function should handle SPARC case correctly.
1516 1516 */
1517 1517 if (!ixgbe_find_mac_address(ixgbe)) {
1518 1518 ixgbe_error(ixgbe, "Failed to get the mac address");
1519 1519 return (IXGBE_FAILURE);
1520 1520 }
1521 1521
1522 1522 /*
1523 1523 * Validate the mac address
1524 1524 */
1525 1525 (void) ixgbe_init_rx_addrs(hw);
1526 1526 if (!is_valid_mac_addr(hw->mac.addr)) {
1527 1527 ixgbe_error(ixgbe, "Invalid mac address");
1528 1528 return (IXGBE_FAILURE);
1529 1529 }
1530 1530
1531 1531 /*
1532 1532 * Re-enable relaxed ordering for performance. It is disabled
1533 1533 * by default in the hardware init.
1534 1534 */
1535 1535 if (ixgbe->relax_order_enable == B_TRUE)
1536 1536 ixgbe_enable_relaxed_ordering(hw);
1537 1537
1538 1538 /*
1539 1539 * Setup adapter interrupt vectors
1540 1540 */
1541 1541 ixgbe_setup_adapter_vector(ixgbe);
1542 1542
1543 1543 /*
1544 1544 * Initialize unicast addresses.
1545 1545 */
1546 1546 ixgbe_init_unicst(ixgbe);
1547 1547
1548 1548 /*
1549 1549 * Setup and initialize the mctable structures.
1550 1550 */
1551 1551 ixgbe_setup_multicst(ixgbe);
1552 1552
1553 1553 /*
1554 1554 * Set interrupt throttling rate
1555 1555 */
1556 1556 for (i = 0; i < ixgbe->intr_cnt; i++) {
1557 1557 IXGBE_WRITE_REG(hw, IXGBE_EITR(i), ixgbe->intr_throttling[i]);
1558 1558 }
1559 1559
1560 1560 /*
1561 1561 * Disable Wake-on-LAN
1562 1562 */
1563 1563 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
1564 1564
1565 1565 /*
1566 1566 * Some adapters offer Energy Efficient Ethernet (EEE) support.
1567 1567 * Due to issues with EEE in e1000g/igb, we disable this by default
1568 1568 * as a precautionary measure.
1569 1569 *
1570 1570 * Currently, this is present on a number of the X550 family parts.
1571 1571 */
1572 1572 (void) ixgbe_setup_eee(hw, B_FALSE);
1573 1573
1574 1574 /*
1575 1575 * Turn on any present SFP Tx laser
1576 1576 */
1577 1577 ixgbe_enable_tx_laser(hw);
1578 1578
1579 1579 /*
1580 1580 * Power on the PHY
1581 1581 */
1582 1582 (void) ixgbe_set_phy_power(hw, B_TRUE);
1583 1583
1584 1584 /*
1585 1585 * Save the state of the PHY
1586 1586 */
1587 1587 ixgbe_get_hw_state(ixgbe);
1588 1588
1589 1589 /*
1590 1590 * Make sure driver has control
1591 1591 */
1592 1592 ixgbe_get_driver_control(hw);
1593 1593
1594 1594 return (IXGBE_SUCCESS);
1595 1595 }
1596 1596
1597 1597 /*
1598 1598 * ixgbe_chip_stop - Stop the chipset hardware
1599 1599 */
1600 1600 static void
1601 1601 ixgbe_chip_stop(ixgbe_t *ixgbe)
1602 1602 {
1603 1603 struct ixgbe_hw *hw = &ixgbe->hw;
1604 1604 int rv;
1605 1605
1606 1606 ASSERT(mutex_owned(&ixgbe->gen_lock));
1607 1607
1608 1608 /*
1609 1609 * Stop interupt generation and disable Tx unit
1610 1610 */
1611 1611 hw->adapter_stopped = B_FALSE;
1612 1612 (void) ixgbe_stop_adapter(hw);
1613 1613
1614 1614 /*
1615 1615 * Reset the chipset
1616 1616 */
1617 1617 (void) ixgbe_reset_hw(hw);
1618 1618
1619 1619 /*
1620 1620 * Reset PHY
1621 1621 */
1622 1622 (void) ixgbe_reset_phy(hw);
1623 1623
1624 1624 /*
1625 1625 * Enter LPLU (Low Power, Link Up) mode, if available. Avoid resetting
1626 1626 * the PHY while doing so. Else, just power down the PHY.
1627 1627 */
1628 1628 if (hw->phy.ops.enter_lplu != NULL) {
1629 1629 hw->phy.reset_disable = B_TRUE;
1630 1630 rv = hw->phy.ops.enter_lplu(hw);
1631 1631 if (rv != IXGBE_SUCCESS)
1632 1632 ixgbe_error(ixgbe, "Error while entering LPLU: %d", rv);
1633 1633 hw->phy.reset_disable = B_FALSE;
1634 1634 } else {
1635 1635 (void) ixgbe_set_phy_power(hw, B_FALSE);
1636 1636 }
1637 1637
1638 1638 /*
1639 1639 * Turn off any present SFP Tx laser
1640 1640 * Expected for health and safety reasons
1641 1641 */
1642 1642 ixgbe_disable_tx_laser(hw);
1643 1643
1644 1644 /*
1645 1645 * Tell firmware driver is no longer in control
1646 1646 */
1647 1647 ixgbe_release_driver_control(hw);
1648 1648
1649 1649 }
1650 1650
1651 1651 /*
1652 1652 * ixgbe_reset - Reset the chipset and re-start the driver.
1653 1653 *
1654 1654 * It involves stopping and re-starting the chipset,
1655 1655 * and re-configuring the rx/tx rings.
1656 1656 */
1657 1657 static int
1658 1658 ixgbe_reset(ixgbe_t *ixgbe)
1659 1659 {
1660 1660 int i;
1661 1661
1662 1662 /*
1663 1663 * Disable and stop the watchdog timer
1664 1664 */
1665 1665 ixgbe_disable_watchdog_timer(ixgbe);
1666 1666
1667 1667 mutex_enter(&ixgbe->gen_lock);
1668 1668
1669 1669 ASSERT(ixgbe->ixgbe_state & IXGBE_STARTED);
1670 1670 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
1671 1671
1672 1672 ixgbe_stop(ixgbe, B_FALSE);
1673 1673
1674 1674 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1675 1675 mutex_exit(&ixgbe->gen_lock);
1676 1676 return (IXGBE_FAILURE);
1677 1677 }
1678 1678
1679 1679 /*
1680 1680 * After resetting, need to recheck the link status.
1681 1681 */
1682 1682 ixgbe->link_check_complete = B_FALSE;
1683 1683 ixgbe->link_check_hrtime = gethrtime() +
1684 1684 (IXGBE_LINK_UP_TIME * 100000000ULL);
1685 1685
1686 1686 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STARTED);
1687 1687
1688 1688 if (!(ixgbe->ixgbe_state & IXGBE_SUSPENDED)) {
1689 1689 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1690 1690 mac_tx_ring_update(ixgbe->mac_hdl,
1691 1691 ixgbe->tx_rings[i].ring_handle);
1692 1692 }
1693 1693 }
1694 1694
1695 1695 mutex_exit(&ixgbe->gen_lock);
1696 1696
1697 1697 /*
1698 1698 * Enable and start the watchdog timer
1699 1699 */
1700 1700 ixgbe_enable_watchdog_timer(ixgbe);
1701 1701
1702 1702 return (IXGBE_SUCCESS);
1703 1703 }
1704 1704
1705 1705 /*
1706 1706 * ixgbe_tx_clean - Clean the pending transmit packets and DMA resources.
1707 1707 */
1708 1708 static void
1709 1709 ixgbe_tx_clean(ixgbe_t *ixgbe)
1710 1710 {
1711 1711 ixgbe_tx_ring_t *tx_ring;
1712 1712 tx_control_block_t *tcb;
1713 1713 link_list_t pending_list;
1714 1714 uint32_t desc_num;
1715 1715 int i, j;
1716 1716
1717 1717 LINK_LIST_INIT(&pending_list);
1718 1718
1719 1719 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1720 1720 tx_ring = &ixgbe->tx_rings[i];
1721 1721
1722 1722 mutex_enter(&tx_ring->recycle_lock);
1723 1723
1724 1724 /*
1725 1725 * Clean the pending tx data - the pending packets in the
1726 1726 * work_list that have no chances to be transmitted again.
1727 1727 *
1728 1728 * We must ensure the chipset is stopped or the link is down
1729 1729 * before cleaning the transmit packets.
1730 1730 */
1731 1731 desc_num = 0;
1732 1732 for (j = 0; j < tx_ring->ring_size; j++) {
1733 1733 tcb = tx_ring->work_list[j];
1734 1734 if (tcb != NULL) {
1735 1735 desc_num += tcb->desc_num;
1736 1736
1737 1737 tx_ring->work_list[j] = NULL;
1738 1738
1739 1739 ixgbe_free_tcb(tcb);
1740 1740
1741 1741 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1742 1742 }
1743 1743 }
1744 1744
1745 1745 if (desc_num > 0) {
1746 1746 atomic_add_32(&tx_ring->tbd_free, desc_num);
1747 1747 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1748 1748
1749 1749 /*
1750 1750 * Reset the head and tail pointers of the tbd ring;
1751 1751 * Reset the writeback head if it's enable.
1752 1752 */
1753 1753 tx_ring->tbd_head = 0;
1754 1754 tx_ring->tbd_tail = 0;
1755 1755 if (ixgbe->tx_head_wb_enable)
1756 1756 *tx_ring->tbd_head_wb = 0;
1757 1757
1758 1758 IXGBE_WRITE_REG(&ixgbe->hw,
1759 1759 IXGBE_TDH(tx_ring->index), 0);
1760 1760 IXGBE_WRITE_REG(&ixgbe->hw,
1761 1761 IXGBE_TDT(tx_ring->index), 0);
1762 1762 }
1763 1763
1764 1764 mutex_exit(&tx_ring->recycle_lock);
1765 1765
1766 1766 /*
1767 1767 * Add the tx control blocks in the pending list to
1768 1768 * the free list.
1769 1769 */
1770 1770 ixgbe_put_free_list(tx_ring, &pending_list);
1771 1771 }
1772 1772 }
1773 1773
1774 1774 /*
1775 1775 * ixgbe_tx_drain - Drain the tx rings to allow pending packets to be
1776 1776 * transmitted.
1777 1777 */
1778 1778 static boolean_t
1779 1779 ixgbe_tx_drain(ixgbe_t *ixgbe)
1780 1780 {
1781 1781 ixgbe_tx_ring_t *tx_ring;
1782 1782 boolean_t done;
1783 1783 int i, j;
1784 1784
1785 1785 /*
1786 1786 * Wait for a specific time to allow pending tx packets
1787 1787 * to be transmitted.
1788 1788 *
1789 1789 * Check the counter tbd_free to see if transmission is done.
1790 1790 * No lock protection is needed here.
1791 1791 *
1792 1792 * Return B_TRUE if all pending packets have been transmitted;
1793 1793 * Otherwise return B_FALSE;
1794 1794 */
1795 1795 for (i = 0; i < TX_DRAIN_TIME; i++) {
1796 1796
1797 1797 done = B_TRUE;
1798 1798 for (j = 0; j < ixgbe->num_tx_rings; j++) {
1799 1799 tx_ring = &ixgbe->tx_rings[j];
1800 1800 done = done &&
1801 1801 (tx_ring->tbd_free == tx_ring->ring_size);
1802 1802 }
1803 1803
1804 1804 if (done)
1805 1805 break;
1806 1806
1807 1807 msec_delay(1);
1808 1808 }
1809 1809
1810 1810 return (done);
1811 1811 }
1812 1812
1813 1813 /*
1814 1814 * ixgbe_rx_drain - Wait for all rx buffers to be released by upper layer.
1815 1815 */
1816 1816 static boolean_t
1817 1817 ixgbe_rx_drain(ixgbe_t *ixgbe)
1818 1818 {
1819 1819 boolean_t done = B_TRUE;
1820 1820 int i;
1821 1821
1822 1822 /*
1823 1823 * Polling the rx free list to check if those rx buffers held by
1824 1824 * the upper layer are released.
1825 1825 *
1826 1826 * Check the counter rcb_free to see if all pending buffers are
1827 1827 * released. No lock protection is needed here.
1828 1828 *
1829 1829 * Return B_TRUE if all pending buffers have been released;
1830 1830 * Otherwise return B_FALSE;
1831 1831 */
1832 1832 for (i = 0; i < RX_DRAIN_TIME; i++) {
1833 1833 done = (ixgbe->rcb_pending == 0);
1834 1834
1835 1835 if (done)
1836 1836 break;
1837 1837
1838 1838 msec_delay(1);
1839 1839 }
1840 1840
1841 1841 return (done);
1842 1842 }
1843 1843
1844 1844 /*
1845 1845 * ixgbe_start - Start the driver/chipset.
1846 1846 */
1847 1847 int
1848 1848 ixgbe_start(ixgbe_t *ixgbe, boolean_t alloc_buffer)
1849 1849 {
1850 1850 struct ixgbe_hw *hw = &ixgbe->hw;
1851 1851 int i;
1852 1852
1853 1853 ASSERT(mutex_owned(&ixgbe->gen_lock));
1854 1854
1855 1855 if (alloc_buffer) {
1856 1856 if (ixgbe_alloc_rx_data(ixgbe) != IXGBE_SUCCESS) {
1857 1857 ixgbe_error(ixgbe,
1858 1858 "Failed to allocate software receive rings");
1859 1859 return (IXGBE_FAILURE);
1860 1860 }
1861 1861
1862 1862 /* Allocate buffers for all the rx/tx rings */
1863 1863 if (ixgbe_alloc_dma(ixgbe) != IXGBE_SUCCESS) {
1864 1864 ixgbe_error(ixgbe, "Failed to allocate DMA resource");
1865 1865 return (IXGBE_FAILURE);
1866 1866 }
1867 1867
1868 1868 ixgbe->tx_ring_init = B_TRUE;
1869 1869 } else {
1870 1870 ixgbe->tx_ring_init = B_FALSE;
1871 1871 }
1872 1872
1873 1873 for (i = 0; i < ixgbe->num_rx_rings; i++)
1874 1874 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1875 1875 for (i = 0; i < ixgbe->num_tx_rings; i++)
1876 1876 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1877 1877
1878 1878 /*
1879 1879 * Start the chipset hardware
1880 1880 */
1881 1881 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1882 1882 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1883 1883 goto start_failure;
1884 1884 }
1885 1885
1886 1886 /*
1887 1887 * Configure link now for X550
1888 1888 *
1889 1889 * X550 possesses a LPLU (Low-Power Link Up) mode which keeps the
1890 1890 * resting state of the adapter at a 1Gb FDX speed. Prior to the X550,
1891 1891 * the resting state of the link would be the maximum speed that
1892 1892 * autonegotiation will allow (usually 10Gb, infrastructure allowing)
1893 1893 * so we never bothered with explicitly setting the link to 10Gb as it
1894 1894 * would already be at that state on driver attach. With X550, we must
1895 1895 * trigger a re-negotiation of the link in order to switch from a LPLU
1896 1896 * 1Gb link to 10Gb (cable and link partner permitting.)
1897 1897 */
1898 1898 if (hw->mac.type == ixgbe_mac_X550 ||
1899 1899 hw->mac.type == ixgbe_mac_X550EM_a ||
1900 1900 hw->mac.type == ixgbe_mac_X550EM_x) {
1901 1901 (void) ixgbe_driver_setup_link(ixgbe, B_TRUE);
1902 1902 ixgbe_get_hw_state(ixgbe);
1903 1903 }
1904 1904
1905 1905 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1906 1906 goto start_failure;
1907 1907 }
1908 1908
1909 1909 /*
1910 1910 * Setup the rx/tx rings
1911 1911 */
1912 1912 ixgbe_setup_rings(ixgbe);
1913 1913
1914 1914 /*
1915 1915 * ixgbe_start() will be called when resetting, however if reset
1916 1916 * happens, we need to clear the ERROR, STALL and OVERTEMP flags
1917 1917 * before enabling the interrupts.
1918 1918 */
1919 1919 atomic_and_32(&ixgbe->ixgbe_state, ~(IXGBE_ERROR
1920 1920 | IXGBE_STALL| IXGBE_OVERTEMP));
1921 1921
1922 1922 /*
1923 1923 * Enable adapter interrupts
1924 1924 * The interrupts must be enabled after the driver state is START
1925 1925 */
1926 1926 ixgbe_enable_adapter_interrupts(ixgbe);
1927 1927
1928 1928 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1929 1929 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1930 1930 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1931 1931 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1932 1932
1933 1933 return (IXGBE_SUCCESS);
1934 1934
1935 1935 start_failure:
1936 1936 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1937 1937 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1938 1938 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1939 1939 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1940 1940
1941 1941 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1942 1942
1943 1943 return (IXGBE_FAILURE);
1944 1944 }
1945 1945
1946 1946 /*
1947 1947 * ixgbe_stop - Stop the driver/chipset.
1948 1948 */
1949 1949 void
1950 1950 ixgbe_stop(ixgbe_t *ixgbe, boolean_t free_buffer)
1951 1951 {
1952 1952 int i;
1953 1953
1954 1954 ASSERT(mutex_owned(&ixgbe->gen_lock));
1955 1955
1956 1956 /*
1957 1957 * Disable the adapter interrupts
1958 1958 */
1959 1959 ixgbe_disable_adapter_interrupts(ixgbe);
1960 1960
1961 1961 /*
1962 1962 * Drain the pending tx packets
1963 1963 */
1964 1964 (void) ixgbe_tx_drain(ixgbe);
1965 1965
1966 1966 for (i = 0; i < ixgbe->num_rx_rings; i++)
1967 1967 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1968 1968 for (i = 0; i < ixgbe->num_tx_rings; i++)
1969 1969 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1970 1970
1971 1971 /*
1972 1972 * Stop the chipset hardware
1973 1973 */
1974 1974 ixgbe_chip_stop(ixgbe);
1975 1975
1976 1976 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1977 1977 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1978 1978 }
1979 1979
1980 1980 /*
1981 1981 * Clean the pending tx data/resources
1982 1982 */
1983 1983 ixgbe_tx_clean(ixgbe);
1984 1984
1985 1985 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1986 1986 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1987 1987 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1988 1988 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1989 1989
1990 1990 if (ixgbe->link_state == LINK_STATE_UP) {
1991 1991 ixgbe->link_state = LINK_STATE_UNKNOWN;
1992 1992 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
1993 1993 }
1994 1994
1995 1995 if (free_buffer) {
1996 1996 /*
1997 1997 * Release the DMA/memory resources of rx/tx rings
1998 1998 */
1999 1999 ixgbe_free_dma(ixgbe);
2000 2000 ixgbe_free_rx_data(ixgbe);
2001 2001 }
2002 2002 }
2003 2003
2004 2004 /*
2005 2005 * ixgbe_cbfunc - Driver interface for generic DDI callbacks
2006 2006 */
2007 2007 /* ARGSUSED */
2008 2008 static int
2009 2009 ixgbe_cbfunc(dev_info_t *dip, ddi_cb_action_t cbaction, void *cbarg,
2010 2010 void *arg1, void *arg2)
2011 2011 {
2012 2012 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
2013 2013
2014 2014 switch (cbaction) {
2015 2015 /* IRM callback */
2016 2016 int count;
2017 2017 case DDI_CB_INTR_ADD:
2018 2018 case DDI_CB_INTR_REMOVE:
2019 2019 count = (int)(uintptr_t)cbarg;
2020 2020 ASSERT(ixgbe->intr_type == DDI_INTR_TYPE_MSIX);
2021 2021 DTRACE_PROBE2(ixgbe__irm__callback, int, count,
2022 2022 int, ixgbe->intr_cnt);
2023 2023 if (ixgbe_intr_adjust(ixgbe, cbaction, count) !=
2024 2024 DDI_SUCCESS) {
2025 2025 ixgbe_error(ixgbe,
2026 2026 "IRM CB: Failed to adjust interrupts");
2027 2027 goto cb_fail;
2028 2028 }
2029 2029 break;
2030 2030 default:
2031 2031 IXGBE_DEBUGLOG_1(ixgbe, "DDI CB: action 0x%x NOT supported",
2032 2032 cbaction);
2033 2033 return (DDI_ENOTSUP);
2034 2034 }
2035 2035 return (DDI_SUCCESS);
2036 2036 cb_fail:
2037 2037 return (DDI_FAILURE);
2038 2038 }
2039 2039
2040 2040 /*
2041 2041 * ixgbe_intr_adjust - Adjust interrupt to respond to IRM request.
2042 2042 */
2043 2043 static int
2044 2044 ixgbe_intr_adjust(ixgbe_t *ixgbe, ddi_cb_action_t cbaction, int count)
2045 2045 {
2046 2046 int i, rc, actual;
2047 2047
2048 2048 if (count == 0)
2049 2049 return (DDI_SUCCESS);
2050 2050
2051 2051 if ((cbaction == DDI_CB_INTR_ADD &&
2052 2052 ixgbe->intr_cnt + count > ixgbe->intr_cnt_max) ||
2053 2053 (cbaction == DDI_CB_INTR_REMOVE &&
2054 2054 ixgbe->intr_cnt - count < ixgbe->intr_cnt_min))
2055 2055 return (DDI_FAILURE);
2056 2056
2057 2057 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
2058 2058 return (DDI_FAILURE);
2059 2059 }
2060 2060
2061 2061 for (i = 0; i < ixgbe->num_rx_rings; i++)
2062 2062 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle, NULL);
2063 2063 for (i = 0; i < ixgbe->num_tx_rings; i++)
2064 2064 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle, NULL);
2065 2065
2066 2066 mutex_enter(&ixgbe->gen_lock);
2067 2067 ixgbe->ixgbe_state &= ~IXGBE_STARTED;
2068 2068 ixgbe->ixgbe_state |= IXGBE_INTR_ADJUST;
2069 2069 ixgbe->ixgbe_state |= IXGBE_SUSPENDED;
2070 2070 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
2071 2071
2072 2072 ixgbe_stop(ixgbe, B_FALSE);
2073 2073 /*
2074 2074 * Disable interrupts
2075 2075 */
2076 2076 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
2077 2077 rc = ixgbe_disable_intrs(ixgbe);
2078 2078 ASSERT(rc == IXGBE_SUCCESS);
2079 2079 }
2080 2080 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ENABLE_INTR;
2081 2081
2082 2082 /*
2083 2083 * Remove interrupt handlers
2084 2084 */
2085 2085 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
2086 2086 ixgbe_rem_intr_handlers(ixgbe);
2087 2087 }
2088 2088 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ADD_INTR;
2089 2089
2090 2090 /*
2091 2091 * Clear vect_map
2092 2092 */
2093 2093 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
2094 2094 switch (cbaction) {
2095 2095 case DDI_CB_INTR_ADD:
2096 2096 rc = ddi_intr_alloc(ixgbe->dip, ixgbe->htable,
2097 2097 DDI_INTR_TYPE_MSIX, ixgbe->intr_cnt, count, &actual,
2098 2098 DDI_INTR_ALLOC_NORMAL);
2099 2099 if (rc != DDI_SUCCESS || actual != count) {
2100 2100 ixgbe_log(ixgbe, "Adjust interrupts failed."
2101 2101 "return: %d, irm cb size: %d, actual: %d",
2102 2102 rc, count, actual);
2103 2103 goto intr_adjust_fail;
2104 2104 }
2105 2105 ixgbe->intr_cnt += count;
2106 2106 break;
2107 2107
2108 2108 case DDI_CB_INTR_REMOVE:
2109 2109 for (i = ixgbe->intr_cnt - count;
2110 2110 i < ixgbe->intr_cnt; i ++) {
2111 2111 rc = ddi_intr_free(ixgbe->htable[i]);
2112 2112 ixgbe->htable[i] = NULL;
2113 2113 if (rc != DDI_SUCCESS) {
2114 2114 ixgbe_log(ixgbe, "Adjust interrupts failed."
2115 2115 "return: %d, irm cb size: %d, actual: %d",
2116 2116 rc, count, actual);
2117 2117 goto intr_adjust_fail;
2118 2118 }
2119 2119 }
2120 2120 ixgbe->intr_cnt -= count;
2121 2121 break;
2122 2122 }
2123 2123
2124 2124 /*
2125 2125 * Get priority for first vector, assume remaining are all the same
2126 2126 */
2127 2127 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
2128 2128 if (rc != DDI_SUCCESS) {
2129 2129 ixgbe_log(ixgbe,
2130 2130 "Get interrupt priority failed: %d", rc);
2131 2131 goto intr_adjust_fail;
2132 2132 }
2133 2133 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
2134 2134 if (rc != DDI_SUCCESS) {
2135 2135 ixgbe_log(ixgbe, "Get interrupt cap failed: %d", rc);
2136 2136 goto intr_adjust_fail;
2137 2137 }
2138 2138 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
2139 2139
2140 2140 /*
2141 2141 * Map rings to interrupt vectors
2142 2142 */
2143 2143 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
2144 2144 ixgbe_error(ixgbe,
2145 2145 "IRM CB: Failed to map interrupts to vectors");
2146 2146 goto intr_adjust_fail;
2147 2147 }
2148 2148
2149 2149 /*
2150 2150 * Add interrupt handlers
2151 2151 */
2152 2152 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
2153 2153 ixgbe_error(ixgbe, "IRM CB: Failed to add interrupt handlers");
2154 2154 goto intr_adjust_fail;
2155 2155 }
2156 2156 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
2157 2157
2158 2158 /*
2159 2159 * Now that mutex locks are initialized, and the chip is also
2160 2160 * initialized, enable interrupts.
2161 2161 */
2162 2162 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
2163 2163 ixgbe_error(ixgbe, "IRM CB: Failed to enable DDI interrupts");
2164 2164 goto intr_adjust_fail;
2165 2165 }
2166 2166 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
2167 2167 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
2168 2168 ixgbe_error(ixgbe, "IRM CB: Failed to start");
2169 2169 goto intr_adjust_fail;
2170 2170 }
2171 2171 ixgbe->ixgbe_state &= ~IXGBE_INTR_ADJUST;
2172 2172 ixgbe->ixgbe_state &= ~IXGBE_SUSPENDED;
2173 2173 ixgbe->ixgbe_state |= IXGBE_STARTED;
2174 2174 mutex_exit(&ixgbe->gen_lock);
2175 2175
2176 2176 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2177 2177 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle,
2178 2178 ixgbe->htable[ixgbe->rx_rings[i].intr_vector]);
2179 2179 }
2180 2180 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2181 2181 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle,
2182 2182 ixgbe->htable[ixgbe->tx_rings[i].intr_vector]);
2183 2183 }
2184 2184
2185 2185 /* Wakeup all Tx rings */
2186 2186 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2187 2187 mac_tx_ring_update(ixgbe->mac_hdl,
2188 2188 ixgbe->tx_rings[i].ring_handle);
2189 2189 }
2190 2190
2191 2191 IXGBE_DEBUGLOG_3(ixgbe,
2192 2192 "IRM CB: interrupts new value: 0x%x(0x%x:0x%x).",
2193 2193 ixgbe->intr_cnt, ixgbe->intr_cnt_min, ixgbe->intr_cnt_max);
2194 2194 return (DDI_SUCCESS);
2195 2195
2196 2196 intr_adjust_fail:
2197 2197 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
2198 2198 mutex_exit(&ixgbe->gen_lock);
2199 2199 return (DDI_FAILURE);
2200 2200 }
2201 2201
2202 2202 /*
2203 2203 * ixgbe_intr_cb_register - Register interrupt callback function.
2204 2204 */
2205 2205 static int
2206 2206 ixgbe_intr_cb_register(ixgbe_t *ixgbe)
2207 2207 {
2208 2208 if (ddi_cb_register(ixgbe->dip, DDI_CB_FLAG_INTR, ixgbe_cbfunc,
2209 2209 ixgbe, NULL, &ixgbe->cb_hdl) != DDI_SUCCESS) {
2210 2210 return (IXGBE_FAILURE);
2211 2211 }
2212 2212 IXGBE_DEBUGLOG_0(ixgbe, "Interrupt callback function registered.");
2213 2213 return (IXGBE_SUCCESS);
2214 2214 }
2215 2215
2216 2216 /*
2217 2217 * ixgbe_alloc_rings - Allocate memory space for rx/tx rings.
2218 2218 */
2219 2219 static int
2220 2220 ixgbe_alloc_rings(ixgbe_t *ixgbe)
2221 2221 {
2222 2222 /*
2223 2223 * Allocate memory space for rx rings
2224 2224 */
2225 2225 ixgbe->rx_rings = kmem_zalloc(
2226 2226 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings,
2227 2227 KM_NOSLEEP);
2228 2228
2229 2229 if (ixgbe->rx_rings == NULL) {
2230 2230 return (IXGBE_FAILURE);
2231 2231 }
2232 2232
2233 2233 /*
2234 2234 * Allocate memory space for tx rings
2235 2235 */
2236 2236 ixgbe->tx_rings = kmem_zalloc(
2237 2237 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings,
2238 2238 KM_NOSLEEP);
2239 2239
2240 2240 if (ixgbe->tx_rings == NULL) {
2241 2241 kmem_free(ixgbe->rx_rings,
2242 2242 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2243 2243 ixgbe->rx_rings = NULL;
2244 2244 return (IXGBE_FAILURE);
2245 2245 }
2246 2246
2247 2247 /*
2248 2248 * Allocate memory space for rx ring groups
2249 2249 */
2250 2250 ixgbe->rx_groups = kmem_zalloc(
2251 2251 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups,
2252 2252 KM_NOSLEEP);
2253 2253
2254 2254 if (ixgbe->rx_groups == NULL) {
2255 2255 kmem_free(ixgbe->rx_rings,
2256 2256 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2257 2257 kmem_free(ixgbe->tx_rings,
2258 2258 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
2259 2259 ixgbe->rx_rings = NULL;
2260 2260 ixgbe->tx_rings = NULL;
2261 2261 return (IXGBE_FAILURE);
2262 2262 }
2263 2263
2264 2264 return (IXGBE_SUCCESS);
2265 2265 }
2266 2266
2267 2267 /*
2268 2268 * ixgbe_free_rings - Free the memory space of rx/tx rings.
2269 2269 */
2270 2270 static void
2271 2271 ixgbe_free_rings(ixgbe_t *ixgbe)
2272 2272 {
2273 2273 if (ixgbe->rx_rings != NULL) {
2274 2274 kmem_free(ixgbe->rx_rings,
2275 2275 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2276 2276 ixgbe->rx_rings = NULL;
2277 2277 }
2278 2278
2279 2279 if (ixgbe->tx_rings != NULL) {
2280 2280 kmem_free(ixgbe->tx_rings,
2281 2281 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
2282 2282 ixgbe->tx_rings = NULL;
2283 2283 }
2284 2284
2285 2285 if (ixgbe->rx_groups != NULL) {
2286 2286 kmem_free(ixgbe->rx_groups,
2287 2287 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups);
2288 2288 ixgbe->rx_groups = NULL;
2289 2289 }
2290 2290 }
2291 2291
2292 2292 static int
2293 2293 ixgbe_alloc_rx_data(ixgbe_t *ixgbe)
2294 2294 {
2295 2295 ixgbe_rx_ring_t *rx_ring;
2296 2296 int i;
2297 2297
2298 2298 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2299 2299 rx_ring = &ixgbe->rx_rings[i];
2300 2300 if (ixgbe_alloc_rx_ring_data(rx_ring) != IXGBE_SUCCESS)
2301 2301 goto alloc_rx_rings_failure;
2302 2302 }
2303 2303 return (IXGBE_SUCCESS);
2304 2304
2305 2305 alloc_rx_rings_failure:
2306 2306 ixgbe_free_rx_data(ixgbe);
2307 2307 return (IXGBE_FAILURE);
2308 2308 }
2309 2309
2310 2310 static void
2311 2311 ixgbe_free_rx_data(ixgbe_t *ixgbe)
2312 2312 {
2313 2313 ixgbe_rx_ring_t *rx_ring;
2314 2314 ixgbe_rx_data_t *rx_data;
2315 2315 int i;
2316 2316
2317 2317 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2318 2318 rx_ring = &ixgbe->rx_rings[i];
2319 2319
2320 2320 mutex_enter(&ixgbe->rx_pending_lock);
2321 2321 rx_data = rx_ring->rx_data;
2322 2322
2323 2323 if (rx_data != NULL) {
2324 2324 rx_data->flag |= IXGBE_RX_STOPPED;
2325 2325
2326 2326 if (rx_data->rcb_pending == 0) {
2327 2327 ixgbe_free_rx_ring_data(rx_data);
2328 2328 rx_ring->rx_data = NULL;
2329 2329 }
2330 2330 }
2331 2331
2332 2332 mutex_exit(&ixgbe->rx_pending_lock);
2333 2333 }
2334 2334 }
2335 2335
2336 2336 /*
2337 2337 * ixgbe_setup_rings - Setup rx/tx rings.
2338 2338 */
2339 2339 static void
2340 2340 ixgbe_setup_rings(ixgbe_t *ixgbe)
2341 2341 {
2342 2342 /*
2343 2343 * Setup the rx/tx rings, including the following:
2344 2344 *
2345 2345 * 1. Setup the descriptor ring and the control block buffers;
2346 2346 * 2. Initialize necessary registers for receive/transmit;
2347 2347 * 3. Initialize software pointers/parameters for receive/transmit;
2348 2348 */
2349 2349 ixgbe_setup_rx(ixgbe);
2350 2350
2351 2351 ixgbe_setup_tx(ixgbe);
2352 2352 }
2353 2353
2354 2354 static void
2355 2355 ixgbe_setup_rx_ring(ixgbe_rx_ring_t *rx_ring)
2356 2356 {
2357 2357 ixgbe_t *ixgbe = rx_ring->ixgbe;
2358 2358 ixgbe_rx_data_t *rx_data = rx_ring->rx_data;
2359 2359 struct ixgbe_hw *hw = &ixgbe->hw;
2360 2360 rx_control_block_t *rcb;
2361 2361 union ixgbe_adv_rx_desc *rbd;
2362 2362 uint32_t size;
2363 2363 uint32_t buf_low;
2364 2364 uint32_t buf_high;
2365 2365 uint32_t reg_val;
2366 2366 int i;
2367 2367
2368 2368 ASSERT(mutex_owned(&rx_ring->rx_lock));
2369 2369 ASSERT(mutex_owned(&ixgbe->gen_lock));
2370 2370
2371 2371 for (i = 0; i < ixgbe->rx_ring_size; i++) {
2372 2372 rcb = rx_data->work_list[i];
2373 2373 rbd = &rx_data->rbd_ring[i];
2374 2374
2375 2375 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
2376 2376 rbd->read.hdr_addr = 0;
2377 2377 }
2378 2378
2379 2379 /*
2380 2380 * Initialize the length register
2381 2381 */
2382 2382 size = rx_data->ring_size * sizeof (union ixgbe_adv_rx_desc);
2383 2383 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rx_ring->hw_index), size);
2384 2384
2385 2385 /*
2386 2386 * Initialize the base address registers
2387 2387 */
2388 2388 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
2389 2389 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
2390 2390 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rx_ring->hw_index), buf_high);
2391 2391 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rx_ring->hw_index), buf_low);
2392 2392
2393 2393 /*
2394 2394 * Setup head & tail pointers
2395 2395 */
2396 2396 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->hw_index),
2397 2397 rx_data->ring_size - 1);
2398 2398 IXGBE_WRITE_REG(hw, IXGBE_RDH(rx_ring->hw_index), 0);
2399 2399
2400 2400 rx_data->rbd_next = 0;
2401 2401 rx_data->lro_first = 0;
2402 2402
2403 2403 /*
2404 2404 * Setup the Receive Descriptor Control Register (RXDCTL)
2405 2405 * PTHRESH=32 descriptors (half the internal cache)
2406 2406 * HTHRESH=0 descriptors (to minimize latency on fetch)
2407 2407 * WTHRESH defaults to 1 (writeback each descriptor)
2408 2408 */
2409 2409 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index));
2410 2410 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */
2411 2411
2412 2412 /* Not a valid value for 82599, X540 or X550 */
2413 2413 if (hw->mac.type == ixgbe_mac_82598EB) {
2414 2414 reg_val |= 0x0020; /* pthresh */
2415 2415 }
2416 2416 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val);
2417 2417
2418 2418 if (hw->mac.type == ixgbe_mac_82599EB ||
2419 2419 hw->mac.type == ixgbe_mac_X540 ||
2420 2420 hw->mac.type == ixgbe_mac_X550 ||
2421 2421 hw->mac.type == ixgbe_mac_X550EM_x ||
2422 2422 hw->mac.type == ixgbe_mac_X550EM_a) {
2423 2423 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2424 2424 reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS);
2425 2425 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2426 2426 }
2427 2427
2428 2428 /*
2429 2429 * Setup the Split and Replication Receive Control Register.
2430 2430 * Set the rx buffer size and the advanced descriptor type.
2431 2431 */
2432 2432 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) |
2433 2433 IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
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2434 2434 reg_val |= IXGBE_SRRCTL_DROP_EN;
2435 2435 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rx_ring->hw_index), reg_val);
2436 2436 }
2437 2437
2438 2438 static void
2439 2439 ixgbe_setup_rx(ixgbe_t *ixgbe)
2440 2440 {
2441 2441 ixgbe_rx_ring_t *rx_ring;
2442 2442 struct ixgbe_hw *hw = &ixgbe->hw;
2443 2443 uint32_t reg_val;
2444 - uint32_t ring_mapping;
2445 - uint32_t i, index;
2444 + uint32_t i;
2446 2445 uint32_t psrtype_rss_bit;
2447 2446
2448 2447 /*
2449 2448 * Ensure that Rx is disabled while setting up
2450 2449 * the Rx unit and Rx descriptor ring(s)
2451 2450 */
2452 2451 ixgbe_disable_rx(hw);
2453 2452
2454 2453 /* PSRTYPE must be configured for 82599 */
2455 2454 if (ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ &&
2456 2455 ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ_RSS) {
2457 2456 reg_val = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
2458 2457 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR;
2459 2458 reg_val |= IXGBE_PSRTYPE_L2HDR;
2460 2459 reg_val |= 0x80000000;
2461 2460 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), reg_val);
2462 2461 } else {
2463 2462 if (ixgbe->num_rx_groups > 32) {
2464 2463 psrtype_rss_bit = 0x20000000;
2465 2464 } else {
2466 2465 psrtype_rss_bit = 0x40000000;
2467 2466 }
2468 2467 for (i = 0; i < ixgbe->capab->max_rx_grp_num; i++) {
2469 2468 reg_val = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
2470 2469 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR;
2471 2470 reg_val |= IXGBE_PSRTYPE_L2HDR;
2472 2471 reg_val |= psrtype_rss_bit;
2473 2472 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(i), reg_val);
2474 2473 }
2475 2474 }
2476 2475
2477 2476 /*
2478 2477 * Set filter control in FCTRL to determine types of packets are passed
2479 2478 * up to the driver.
2480 2479 * - Pass broadcast packets.
2481 2480 * - Do not pass flow control pause frames (82598-specific)
2482 2481 */
2483 2482 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2484 2483 reg_val |= IXGBE_FCTRL_BAM; /* Broadcast Accept Mode */
2485 2484 if (hw->mac.type == ixgbe_mac_82598EB) {
2486 2485 reg_val |= IXGBE_FCTRL_DPF; /* Discard Pause Frames */
2487 2486 }
2488 2487 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_val);
2489 2488
2490 2489 /*
2491 2490 * Hardware checksum settings
2492 2491 */
2493 2492 if (ixgbe->rx_hcksum_enable) {
2494 2493 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2495 2494 reg_val |= IXGBE_RXCSUM_IPPCSE; /* IP checksum */
2496 2495 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, reg_val);
2497 2496 }
2498 2497
2499 2498 /*
2500 2499 * Setup VMDq and RSS for multiple receive queues
2501 2500 */
2502 2501 switch (ixgbe->classify_mode) {
2503 2502 case IXGBE_CLASSIFY_RSS:
2504 2503 /*
2505 2504 * One group, only RSS is needed when more than
2506 2505 * one ring enabled.
2507 2506 */
2508 2507 ixgbe_setup_rss(ixgbe);
2509 2508 break;
2510 2509
2511 2510 case IXGBE_CLASSIFY_VMDQ:
2512 2511 /*
2513 2512 * Multiple groups, each group has one ring,
2514 2513 * only VMDq is needed.
2515 2514 */
2516 2515 ixgbe_setup_vmdq(ixgbe);
2517 2516 break;
2518 2517
2519 2518 case IXGBE_CLASSIFY_VMDQ_RSS:
2520 2519 /*
2521 2520 * Multiple groups and multiple rings, both
2522 2521 * VMDq and RSS are needed.
2523 2522 */
2524 2523 ixgbe_setup_vmdq_rss(ixgbe);
2525 2524 break;
2526 2525
2527 2526 default:
2528 2527 break;
2529 2528 }
2530 2529
2531 2530 /*
2532 2531 * Enable the receive unit. This must be done after filter
2533 2532 * control is set in FCTRL. On 82598, we disable the descriptor monitor.
2534 2533 * 82598 is the only adapter which defines this RXCTRL option.
2535 2534 */
2536 2535 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2537 2536 if (hw->mac.type == ixgbe_mac_82598EB)
2538 2537 reg_val |= IXGBE_RXCTRL_DMBYPS; /* descriptor monitor bypass */
2539 2538 reg_val |= IXGBE_RXCTRL_RXEN;
2540 2539 (void) ixgbe_enable_rx_dma(hw, reg_val);
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2541 2540
2542 2541 /*
2543 2542 * ixgbe_setup_rx_ring must be called after configuring RXCTRL
2544 2543 */
2545 2544 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2546 2545 rx_ring = &ixgbe->rx_rings[i];
2547 2546 ixgbe_setup_rx_ring(rx_ring);
2548 2547 }
2549 2548
2550 2549 /*
2551 - * Setup the per-ring statistics mapping.
2550 + * The 82598 controller gives us the RNBC (Receive No Buffer
2551 + * Count) register to determine the number of frames dropped
2552 + * due to no available descriptors on the destination queue.
2553 + * However, this register was removed starting with 82599 and
2554 + * it was replaced with the RQSMR/QPRDC registers. The nice
2555 + * thing about the new registers is that they allow you to map
2556 + * groups of queues to specific stat registers. The bad thing
2557 + * is there are only 16 slots in the stat registers, so this
2558 + * won't work when we have 32 Rx groups. Instead, we map all
2559 + * queues to the zero slot of the stat registers, giving us a
2560 + * global counter at QPRDC[0] (with the equivalent semantics
2561 + * of RNBC). Perhaps future controllers will have more slots
2562 + * and we can implement per-group counters.
2552 2563 */
2553 - ring_mapping = 0;
2554 2564 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2555 - index = ixgbe->rx_rings[i].hw_index;
2556 - ring_mapping = IXGBE_READ_REG(hw, IXGBE_RQSMR(index >> 2));
2557 - ring_mapping |= (i & 0xF) << (8 * (index & 0x3));
2558 - IXGBE_WRITE_REG(hw, IXGBE_RQSMR(index >> 2), ring_mapping);
2565 + uint32_t index = ixgbe->rx_rings[i].hw_index;
2566 + IXGBE_WRITE_REG(hw, IXGBE_RQSMR(index >> 2), 0);
2559 2567 }
2560 2568
2561 2569 /*
2562 2570 * The Max Frame Size in MHADD/MAXFRS will be internally increased
2563 2571 * by four bytes if the packet has a VLAN field, so includes MTU,
2564 2572 * ethernet header and frame check sequence.
2565 2573 * Register is MAXFRS in 82599.
2566 2574 */
2567 2575 reg_val = IXGBE_READ_REG(hw, IXGBE_MHADD);
2568 2576 reg_val &= ~IXGBE_MHADD_MFS_MASK;
2569 2577 reg_val |= (ixgbe->default_mtu + sizeof (struct ether_header)
2570 2578 + ETHERFCSL) << IXGBE_MHADD_MFS_SHIFT;
2571 2579 IXGBE_WRITE_REG(hw, IXGBE_MHADD, reg_val);
2572 2580
2573 2581 /*
2574 2582 * Setup Jumbo Frame enable bit
2575 2583 */
2576 2584 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2577 2585 if (ixgbe->default_mtu > ETHERMTU)
2578 2586 reg_val |= IXGBE_HLREG0_JUMBOEN;
2579 2587 else
2580 2588 reg_val &= ~IXGBE_HLREG0_JUMBOEN;
2581 2589 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val);
2582 2590
2583 2591 /*
2584 2592 * Setup RSC for multiple receive queues.
2585 2593 */
2586 2594 if (ixgbe->lro_enable) {
2587 2595 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2588 2596 /*
2589 2597 * Make sure rx_buf_size * MAXDESC not greater
2590 2598 * than 65535.
2591 2599 * Intel recommends 4 for MAXDESC field value.
2592 2600 */
2593 2601 reg_val = IXGBE_READ_REG(hw, IXGBE_RSCCTL(i));
2594 2602 reg_val |= IXGBE_RSCCTL_RSCEN;
2595 2603 if (ixgbe->rx_buf_size == IXGBE_PKG_BUF_16k)
2596 2604 reg_val |= IXGBE_RSCCTL_MAXDESC_1;
2597 2605 else
2598 2606 reg_val |= IXGBE_RSCCTL_MAXDESC_4;
2599 2607 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(i), reg_val);
2600 2608 }
2601 2609
2602 2610 reg_val = IXGBE_READ_REG(hw, IXGBE_RSCDBU);
2603 2611 reg_val |= IXGBE_RSCDBU_RSCACKDIS;
2604 2612 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, reg_val);
2605 2613
2606 2614 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2607 2615 reg_val |= IXGBE_RDRXCTL_RSCACKC;
2608 2616 reg_val |= IXGBE_RDRXCTL_FCOE_WRFIX;
2609 2617 reg_val &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2610 2618
2611 2619 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2612 2620 }
2613 2621 }
2614 2622
2615 2623 static void
2616 2624 ixgbe_setup_tx_ring(ixgbe_tx_ring_t *tx_ring)
2617 2625 {
2618 2626 ixgbe_t *ixgbe = tx_ring->ixgbe;
2619 2627 struct ixgbe_hw *hw = &ixgbe->hw;
2620 2628 uint32_t size;
2621 2629 uint32_t buf_low;
2622 2630 uint32_t buf_high;
2623 2631 uint32_t reg_val;
2624 2632
2625 2633 ASSERT(mutex_owned(&tx_ring->tx_lock));
2626 2634 ASSERT(mutex_owned(&ixgbe->gen_lock));
2627 2635
2628 2636 /*
2629 2637 * Initialize the length register
2630 2638 */
2631 2639 size = tx_ring->ring_size * sizeof (union ixgbe_adv_tx_desc);
2632 2640 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(tx_ring->index), size);
2633 2641
2634 2642 /*
2635 2643 * Initialize the base address registers
2636 2644 */
2637 2645 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2638 2646 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2639 2647 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(tx_ring->index), buf_low);
2640 2648 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(tx_ring->index), buf_high);
2641 2649
2642 2650 /*
2643 2651 * Setup head & tail pointers
2644 2652 */
2645 2653 IXGBE_WRITE_REG(hw, IXGBE_TDH(tx_ring->index), 0);
2646 2654 IXGBE_WRITE_REG(hw, IXGBE_TDT(tx_ring->index), 0);
2647 2655
2648 2656 /*
2649 2657 * Setup head write-back
2650 2658 */
2651 2659 if (ixgbe->tx_head_wb_enable) {
2652 2660 /*
2653 2661 * The memory of the head write-back is allocated using
2654 2662 * the extra tbd beyond the tail of the tbd ring.
2655 2663 */
2656 2664 tx_ring->tbd_head_wb = (uint32_t *)
2657 2665 ((uintptr_t)tx_ring->tbd_area.address + size);
2658 2666 *tx_ring->tbd_head_wb = 0;
2659 2667
2660 2668 buf_low = (uint32_t)
2661 2669 (tx_ring->tbd_area.dma_address + size);
2662 2670 buf_high = (uint32_t)
2663 2671 ((tx_ring->tbd_area.dma_address + size) >> 32);
2664 2672
2665 2673 /* Set the head write-back enable bit */
2666 2674 buf_low |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
2667 2675
2668 2676 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(tx_ring->index), buf_low);
2669 2677 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(tx_ring->index), buf_high);
2670 2678
2671 2679 /*
2672 2680 * Turn off relaxed ordering for head write back or it will
2673 2681 * cause problems with the tx recycling
2674 2682 */
2675 2683
2676 2684 reg_val = (hw->mac.type == ixgbe_mac_82598EB) ?
2677 2685 IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(tx_ring->index)) :
2678 2686 IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(tx_ring->index));
2679 2687 reg_val &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
2680 2688 if (hw->mac.type == ixgbe_mac_82598EB) {
2681 2689 IXGBE_WRITE_REG(hw,
2682 2690 IXGBE_DCA_TXCTRL(tx_ring->index), reg_val);
2683 2691 } else {
2684 2692 IXGBE_WRITE_REG(hw,
2685 2693 IXGBE_DCA_TXCTRL_82599(tx_ring->index), reg_val);
2686 2694 }
2687 2695 } else {
2688 2696 tx_ring->tbd_head_wb = NULL;
2689 2697 }
2690 2698
2691 2699 tx_ring->tbd_head = 0;
2692 2700 tx_ring->tbd_tail = 0;
2693 2701 tx_ring->tbd_free = tx_ring->ring_size;
2694 2702
2695 2703 if (ixgbe->tx_ring_init == B_TRUE) {
2696 2704 tx_ring->tcb_head = 0;
2697 2705 tx_ring->tcb_tail = 0;
2698 2706 tx_ring->tcb_free = tx_ring->free_list_size;
2699 2707 }
2700 2708
2701 2709 /*
2702 2710 * Initialize the s/w context structure
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2703 2711 */
2704 2712 bzero(&tx_ring->tx_context, sizeof (ixgbe_tx_context_t));
2705 2713 }
2706 2714
2707 2715 static void
2708 2716 ixgbe_setup_tx(ixgbe_t *ixgbe)
2709 2717 {
2710 2718 struct ixgbe_hw *hw = &ixgbe->hw;
2711 2719 ixgbe_tx_ring_t *tx_ring;
2712 2720 uint32_t reg_val;
2713 - uint32_t ring_mapping;
2714 2721 int i;
2715 2722
2716 2723 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2717 2724 tx_ring = &ixgbe->tx_rings[i];
2718 2725 ixgbe_setup_tx_ring(tx_ring);
2719 2726 }
2720 2727
2721 2728 /*
2722 - * Setup the per-ring statistics mapping.
2729 + * Setup the per-ring statistics mapping. We map all Tx queues
2730 + * to slot 0 to stay consistent with Rx.
2723 2731 */
2724 - ring_mapping = 0;
2725 2732 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2726 - ring_mapping |= (i & 0xF) << (8 * (i & 0x3));
2727 - if ((i & 0x3) == 0x3) {
2728 - switch (hw->mac.type) {
2729 - case ixgbe_mac_82598EB:
2730 - IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2),
2731 - ring_mapping);
2732 - break;
2733 -
2734 - case ixgbe_mac_82599EB:
2735 - case ixgbe_mac_X540:
2736 - case ixgbe_mac_X550:
2737 - case ixgbe_mac_X550EM_x:
2738 - case ixgbe_mac_X550EM_a:
2739 - IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2),
2740 - ring_mapping);
2741 - break;
2742 -
2743 - default:
2744 - break;
2745 - }
2746 -
2747 - ring_mapping = 0;
2748 - }
2749 - }
2750 - if (i & 0x3) {
2751 2733 switch (hw->mac.type) {
2752 2734 case ixgbe_mac_82598EB:
2753 - IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2), ring_mapping);
2735 + IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2), 0);
2754 2736 break;
2755 2737
2756 - case ixgbe_mac_82599EB:
2757 - case ixgbe_mac_X540:
2758 - case ixgbe_mac_X550:
2759 - case ixgbe_mac_X550EM_x:
2760 - case ixgbe_mac_X550EM_a:
2761 - IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2), ring_mapping);
2762 - break;
2763 -
2764 2738 default:
2739 + IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2), 0);
2765 2740 break;
2766 2741 }
2767 2742 }
2768 2743
2769 2744 /*
2770 2745 * Enable CRC appending and TX padding (for short tx frames)
2771 2746 */
2772 2747 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2773 2748 reg_val |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN;
2774 2749 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val);
2775 2750
2776 2751 /*
2777 2752 * enable DMA for 82599, X540 and X550 parts
2778 2753 */
2779 2754 if (hw->mac.type == ixgbe_mac_82599EB ||
2780 2755 hw->mac.type == ixgbe_mac_X540 ||
2781 2756 hw->mac.type == ixgbe_mac_X550 ||
2782 2757 hw->mac.type == ixgbe_mac_X550EM_x ||
2783 2758 hw->mac.type == ixgbe_mac_X550EM_a) {
2784 2759 /* DMATXCTL.TE must be set after all Tx config is complete */
2785 2760 reg_val = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2786 2761 reg_val |= IXGBE_DMATXCTL_TE;
2787 2762 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_val);
2788 2763
2789 2764 /* Disable arbiter to set MTQC */
2790 2765 reg_val = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2791 2766 reg_val |= IXGBE_RTTDCS_ARBDIS;
2792 2767 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
2793 2768 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2794 2769 reg_val &= ~IXGBE_RTTDCS_ARBDIS;
2795 2770 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
2796 2771 }
2797 2772
2798 2773 /*
2799 2774 * Enabling tx queues ..
2800 2775 * For 82599 must be done after DMATXCTL.TE is set
2801 2776 */
2802 2777 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2803 2778 tx_ring = &ixgbe->tx_rings[i];
2804 2779 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->index));
2805 2780 reg_val |= IXGBE_TXDCTL_ENABLE;
2806 2781 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->index), reg_val);
2807 2782 }
2808 2783 }
2809 2784
2810 2785 /*
2811 2786 * ixgbe_setup_rss - Setup receive-side scaling feature.
2812 2787 */
2813 2788 static void
2814 2789 ixgbe_setup_rss(ixgbe_t *ixgbe)
2815 2790 {
2816 2791 struct ixgbe_hw *hw = &ixgbe->hw;
2817 2792 uint32_t mrqc;
2818 2793
2819 2794 /*
2820 2795 * Initialize RETA/ERETA table
2821 2796 */
2822 2797 ixgbe_setup_rss_table(ixgbe);
2823 2798
2824 2799 /*
2825 2800 * Enable RSS & perform hash on these packet types
2826 2801 */
2827 2802 mrqc = IXGBE_MRQC_RSSEN |
2828 2803 IXGBE_MRQC_RSS_FIELD_IPV4 |
2829 2804 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2830 2805 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2831 2806 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2832 2807 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2833 2808 IXGBE_MRQC_RSS_FIELD_IPV6 |
2834 2809 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2835 2810 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2836 2811 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2837 2812 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2838 2813 }
2839 2814
2840 2815 /*
2841 2816 * ixgbe_setup_vmdq - Setup MAC classification feature
2842 2817 */
2843 2818 static void
2844 2819 ixgbe_setup_vmdq(ixgbe_t *ixgbe)
2845 2820 {
2846 2821 struct ixgbe_hw *hw = &ixgbe->hw;
2847 2822 uint32_t vmdctl, i, vtctl;
2848 2823
2849 2824 /*
2850 2825 * Setup the VMDq Control register, enable VMDq based on
2851 2826 * packet destination MAC address:
2852 2827 */
2853 2828 switch (hw->mac.type) {
2854 2829 case ixgbe_mac_82598EB:
2855 2830 /*
2856 2831 * VMDq Enable = 1;
2857 2832 * VMDq Filter = 0; MAC filtering
2858 2833 * Default VMDq output index = 0;
2859 2834 */
2860 2835 vmdctl = IXGBE_VMD_CTL_VMDQ_EN;
2861 2836 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
2862 2837 break;
2863 2838
2864 2839 case ixgbe_mac_82599EB:
2865 2840 case ixgbe_mac_X540:
2866 2841 case ixgbe_mac_X550:
2867 2842 case ixgbe_mac_X550EM_x:
2868 2843 case ixgbe_mac_X550EM_a:
2869 2844 /*
2870 2845 * Enable VMDq-only.
2871 2846 */
2872 2847 vmdctl = IXGBE_MRQC_VMDQEN;
2873 2848 IXGBE_WRITE_REG(hw, IXGBE_MRQC, vmdctl);
2874 2849
2875 2850 for (i = 0; i < hw->mac.num_rar_entries; i++) {
2876 2851 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(i), 0);
2877 2852 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(i), 0);
2878 2853 }
2879 2854
2880 2855 /*
2881 2856 * Enable Virtualization and Replication.
2882 2857 */
2883 2858 vtctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2884 2859 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
2885 2860
2886 2861 /*
2887 2862 * Enable receiving packets to all VFs
2888 2863 */
2889 2864 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL);
2890 2865 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL);
2891 2866 break;
2892 2867
2893 2868 default:
2894 2869 break;
2895 2870 }
2896 2871 }
2897 2872
2898 2873 /*
2899 2874 * ixgbe_setup_vmdq_rss - Setup both vmdq feature and rss feature.
2900 2875 */
2901 2876 static void
2902 2877 ixgbe_setup_vmdq_rss(ixgbe_t *ixgbe)
2903 2878 {
2904 2879 struct ixgbe_hw *hw = &ixgbe->hw;
2905 2880 uint32_t i, mrqc;
2906 2881 uint32_t vtctl, vmdctl;
2907 2882
2908 2883 /*
2909 2884 * Initialize RETA/ERETA table
2910 2885 */
2911 2886 ixgbe_setup_rss_table(ixgbe);
2912 2887
2913 2888 /*
2914 2889 * Enable and setup RSS and VMDq
2915 2890 */
2916 2891 switch (hw->mac.type) {
2917 2892 case ixgbe_mac_82598EB:
2918 2893 /*
2919 2894 * Enable RSS & Setup RSS Hash functions
2920 2895 */
2921 2896 mrqc = IXGBE_MRQC_RSSEN |
2922 2897 IXGBE_MRQC_RSS_FIELD_IPV4 |
2923 2898 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2924 2899 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2925 2900 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2926 2901 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2927 2902 IXGBE_MRQC_RSS_FIELD_IPV6 |
2928 2903 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2929 2904 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2930 2905 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2931 2906 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2932 2907
2933 2908 /*
2934 2909 * Enable and Setup VMDq
2935 2910 * VMDq Filter = 0; MAC filtering
2936 2911 * Default VMDq output index = 0;
2937 2912 */
2938 2913 vmdctl = IXGBE_VMD_CTL_VMDQ_EN;
2939 2914 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
2940 2915 break;
2941 2916
2942 2917 case ixgbe_mac_82599EB:
2943 2918 case ixgbe_mac_X540:
2944 2919 case ixgbe_mac_X550:
2945 2920 case ixgbe_mac_X550EM_x:
2946 2921 case ixgbe_mac_X550EM_a:
2947 2922 /*
2948 2923 * Enable RSS & Setup RSS Hash functions
2949 2924 */
2950 2925 mrqc = IXGBE_MRQC_RSS_FIELD_IPV4 |
2951 2926 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2952 2927 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2953 2928 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2954 2929 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2955 2930 IXGBE_MRQC_RSS_FIELD_IPV6 |
2956 2931 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2957 2932 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2958 2933 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2959 2934
2960 2935 /*
2961 2936 * Enable VMDq+RSS.
2962 2937 */
2963 2938 if (ixgbe->num_rx_groups > 32) {
2964 2939 mrqc = mrqc | IXGBE_MRQC_VMDQRSS64EN;
2965 2940 } else {
2966 2941 mrqc = mrqc | IXGBE_MRQC_VMDQRSS32EN;
2967 2942 }
2968 2943
2969 2944 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2970 2945
2971 2946 for (i = 0; i < hw->mac.num_rar_entries; i++) {
2972 2947 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(i), 0);
2973 2948 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(i), 0);
2974 2949 }
2975 2950 break;
2976 2951
2977 2952 default:
2978 2953 break;
2979 2954
2980 2955 }
2981 2956
2982 2957 if (hw->mac.type == ixgbe_mac_82599EB ||
2983 2958 hw->mac.type == ixgbe_mac_X540 ||
2984 2959 hw->mac.type == ixgbe_mac_X550 ||
2985 2960 hw->mac.type == ixgbe_mac_X550EM_x ||
2986 2961 hw->mac.type == ixgbe_mac_X550EM_a) {
2987 2962 /*
2988 2963 * Enable Virtualization and Replication.
2989 2964 */
2990 2965 vtctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2991 2966 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
2992 2967
2993 2968 /*
2994 2969 * Enable receiving packets to all VFs
2995 2970 */
2996 2971 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL);
2997 2972 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL);
2998 2973 }
2999 2974 }
3000 2975
3001 2976 /*
3002 2977 * ixgbe_setup_rss_table - Setup RSS table
3003 2978 */
3004 2979 static void
3005 2980 ixgbe_setup_rss_table(ixgbe_t *ixgbe)
3006 2981 {
3007 2982 struct ixgbe_hw *hw = &ixgbe->hw;
3008 2983 uint32_t i, j;
3009 2984 uint32_t random;
3010 2985 uint32_t reta;
3011 2986 uint32_t ring_per_group;
3012 2987 uint32_t ring;
3013 2988 uint32_t table_size;
3014 2989 uint32_t index_mult;
3015 2990 uint32_t rxcsum;
3016 2991
3017 2992 /*
3018 2993 * Set multiplier for RETA setup and table size based on MAC type.
3019 2994 * RETA table sizes vary by model:
3020 2995 *
3021 2996 * 82598, 82599, X540: 128 table entries.
3022 2997 * X550: 512 table entries.
3023 2998 */
3024 2999 index_mult = 0x1;
3025 3000 table_size = 128;
3026 3001 switch (ixgbe->hw.mac.type) {
3027 3002 case ixgbe_mac_82598EB:
3028 3003 index_mult = 0x11;
3029 3004 break;
3030 3005 case ixgbe_mac_X550:
3031 3006 case ixgbe_mac_X550EM_x:
3032 3007 case ixgbe_mac_X550EM_a:
3033 3008 table_size = 512;
3034 3009 break;
3035 3010 default:
3036 3011 break;
3037 3012 }
3038 3013
3039 3014 /*
3040 3015 * Fill out RSS redirection table. The configuation of the indices is
3041 3016 * hardware-dependent.
3042 3017 *
3043 3018 * 82598: 8 bits wide containing two 4 bit RSS indices
3044 3019 * 82599, X540: 8 bits wide containing one 4 bit RSS index
3045 3020 * X550: 8 bits wide containing one 6 bit RSS index
3046 3021 */
3047 3022 reta = 0;
3048 3023 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3049 3024
3050 3025 for (i = 0, j = 0; i < table_size; i++, j++) {
3051 3026 if (j == ring_per_group) j = 0;
3052 3027
3053 3028 /*
3054 3029 * The low 8 bits are for hash value (n+0);
3055 3030 * The next 8 bits are for hash value (n+1), etc.
3056 3031 */
3057 3032 ring = (j * index_mult);
3058 3033 reta = reta >> 8;
3059 3034 reta = reta | (((uint32_t)ring) << 24);
3060 3035
3061 3036 if ((i & 3) == 3) {
3062 3037 /*
3063 3038 * The first 128 table entries are programmed into the
3064 3039 * RETA register, with any beyond that (eg; on X550)
3065 3040 * into ERETA.
3066 3041 */
3067 3042 if (i < 128)
3068 3043 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3069 3044 else
3070 3045 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3071 3046 reta);
3072 3047 reta = 0;
3073 3048 }
3074 3049 }
3075 3050
3076 3051 /*
3077 3052 * Fill out hash function seeds with a random constant
3078 3053 */
3079 3054 for (i = 0; i < 10; i++) {
3080 3055 (void) random_get_pseudo_bytes((uint8_t *)&random,
3081 3056 sizeof (uint32_t));
3082 3057 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random);
3083 3058 }
3084 3059
3085 3060 /*
3086 3061 * Disable Packet Checksum to enable RSS for multiple receive queues.
3087 3062 * It is an adapter hardware limitation that Packet Checksum is
3088 3063 * mutually exclusive with RSS.
3089 3064 */
3090 3065 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3091 3066 rxcsum |= IXGBE_RXCSUM_PCSD;
3092 3067 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3093 3068 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3094 3069 }
3095 3070
3096 3071 /*
3097 3072 * ixgbe_init_unicst - Initialize the unicast addresses.
3098 3073 */
3099 3074 static void
3100 3075 ixgbe_init_unicst(ixgbe_t *ixgbe)
3101 3076 {
3102 3077 struct ixgbe_hw *hw = &ixgbe->hw;
3103 3078 uint8_t *mac_addr;
3104 3079 int slot;
3105 3080 /*
3106 3081 * Here we should consider two situations:
3107 3082 *
3108 3083 * 1. Chipset is initialized at the first time,
3109 3084 * Clear all the multiple unicast addresses.
3110 3085 *
3111 3086 * 2. Chipset is reset
3112 3087 * Recover the multiple unicast addresses from the
3113 3088 * software data structure to the RAR registers.
3114 3089 */
3115 3090 if (!ixgbe->unicst_init) {
3116 3091 /*
3117 3092 * Initialize the multiple unicast addresses
3118 3093 */
3119 3094 ixgbe->unicst_total = hw->mac.num_rar_entries;
3120 3095 ixgbe->unicst_avail = ixgbe->unicst_total;
3121 3096 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3122 3097 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
3123 3098 bzero(mac_addr, ETHERADDRL);
3124 3099 (void) ixgbe_set_rar(hw, slot, mac_addr, 0, 0);
3125 3100 ixgbe->unicst_addr[slot].mac.set = 0;
3126 3101 }
3127 3102 ixgbe->unicst_init = B_TRUE;
3128 3103 } else {
3129 3104 /* Re-configure the RAR registers */
3130 3105 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3131 3106 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
3132 3107 if (ixgbe->unicst_addr[slot].mac.set == 1) {
3133 3108 (void) ixgbe_set_rar(hw, slot, mac_addr,
3134 3109 ixgbe->unicst_addr[slot].mac.group_index,
3135 3110 IXGBE_RAH_AV);
3136 3111 } else {
3137 3112 bzero(mac_addr, ETHERADDRL);
3138 3113 (void) ixgbe_set_rar(hw, slot, mac_addr, 0, 0);
3139 3114 }
3140 3115 }
3141 3116 }
3142 3117 }
3143 3118
3144 3119 /*
3145 3120 * ixgbe_unicst_find - Find the slot for the specified unicast address
3146 3121 */
3147 3122 int
3148 3123 ixgbe_unicst_find(ixgbe_t *ixgbe, const uint8_t *mac_addr)
3149 3124 {
3150 3125 int slot;
3151 3126
3152 3127 ASSERT(mutex_owned(&ixgbe->gen_lock));
3153 3128
3154 3129 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3155 3130 if (bcmp(ixgbe->unicst_addr[slot].mac.addr,
3156 3131 mac_addr, ETHERADDRL) == 0)
3157 3132 return (slot);
3158 3133 }
3159 3134
3160 3135 return (-1);
3161 3136 }
3162 3137
3163 3138 /*
3164 3139 * ixgbe_multicst_add - Add a multicst address.
3165 3140 */
3166 3141 int
3167 3142 ixgbe_multicst_add(ixgbe_t *ixgbe, const uint8_t *multiaddr)
3168 3143 {
3169 3144 ASSERT(mutex_owned(&ixgbe->gen_lock));
3170 3145
3171 3146 if ((multiaddr[0] & 01) == 0) {
3172 3147 return (EINVAL);
3173 3148 }
3174 3149
3175 3150 if (ixgbe->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) {
3176 3151 return (ENOENT);
3177 3152 }
3178 3153
3179 3154 bcopy(multiaddr,
3180 3155 &ixgbe->mcast_table[ixgbe->mcast_count], ETHERADDRL);
3181 3156 ixgbe->mcast_count++;
3182 3157
3183 3158 /*
3184 3159 * Update the multicast table in the hardware
3185 3160 */
3186 3161 ixgbe_setup_multicst(ixgbe);
3187 3162
3188 3163 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
3189 3164 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3190 3165 return (EIO);
3191 3166 }
3192 3167
3193 3168 return (0);
3194 3169 }
3195 3170
3196 3171 /*
3197 3172 * ixgbe_multicst_remove - Remove a multicst address.
3198 3173 */
3199 3174 int
3200 3175 ixgbe_multicst_remove(ixgbe_t *ixgbe, const uint8_t *multiaddr)
3201 3176 {
3202 3177 int i;
3203 3178
3204 3179 ASSERT(mutex_owned(&ixgbe->gen_lock));
3205 3180
3206 3181 for (i = 0; i < ixgbe->mcast_count; i++) {
3207 3182 if (bcmp(multiaddr, &ixgbe->mcast_table[i],
3208 3183 ETHERADDRL) == 0) {
3209 3184 for (i++; i < ixgbe->mcast_count; i++) {
3210 3185 ixgbe->mcast_table[i - 1] =
3211 3186 ixgbe->mcast_table[i];
3212 3187 }
3213 3188 ixgbe->mcast_count--;
3214 3189 break;
3215 3190 }
3216 3191 }
3217 3192
3218 3193 /*
3219 3194 * Update the multicast table in the hardware
3220 3195 */
3221 3196 ixgbe_setup_multicst(ixgbe);
3222 3197
3223 3198 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
3224 3199 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3225 3200 return (EIO);
3226 3201 }
3227 3202
3228 3203 return (0);
3229 3204 }
3230 3205
3231 3206 /*
3232 3207 * ixgbe_setup_multicast - Setup multicast data structures.
3233 3208 *
3234 3209 * This routine initializes all of the multicast related structures
3235 3210 * and save them in the hardware registers.
3236 3211 */
3237 3212 static void
3238 3213 ixgbe_setup_multicst(ixgbe_t *ixgbe)
3239 3214 {
3240 3215 uint8_t *mc_addr_list;
3241 3216 uint32_t mc_addr_count;
3242 3217 struct ixgbe_hw *hw = &ixgbe->hw;
3243 3218
3244 3219 ASSERT(mutex_owned(&ixgbe->gen_lock));
3245 3220
3246 3221 ASSERT(ixgbe->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES);
3247 3222
3248 3223 mc_addr_list = (uint8_t *)ixgbe->mcast_table;
3249 3224 mc_addr_count = ixgbe->mcast_count;
3250 3225
3251 3226 /*
3252 3227 * Update the multicast addresses to the MTA registers
3253 3228 */
3254 3229 (void) ixgbe_update_mc_addr_list(hw, mc_addr_list, mc_addr_count,
3255 3230 ixgbe_mc_table_itr, TRUE);
3256 3231 }
3257 3232
3258 3233 /*
3259 3234 * ixgbe_setup_vmdq_rss_conf - Configure vmdq and rss (number and mode).
3260 3235 *
3261 3236 * Configure the rx classification mode (vmdq & rss) and vmdq & rss numbers.
3262 3237 * Different chipsets may have different allowed configuration of vmdq and rss.
3263 3238 */
3264 3239 static void
3265 3240 ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe)
3266 3241 {
3267 3242 struct ixgbe_hw *hw = &ixgbe->hw;
3268 3243 uint32_t ring_per_group;
3269 3244
3270 3245 switch (hw->mac.type) {
3271 3246 case ixgbe_mac_82598EB:
3272 3247 /*
3273 3248 * 82598 supports the following combination:
3274 3249 * vmdq no. x rss no.
3275 3250 * [5..16] x 1
3276 3251 * [1..4] x [1..16]
3277 3252 * However 8 rss queue per pool (vmdq) is sufficient for
3278 3253 * most cases.
3279 3254 */
3280 3255 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3281 3256 if (ixgbe->num_rx_groups > 4) {
3282 3257 ixgbe->num_rx_rings = ixgbe->num_rx_groups;
3283 3258 } else {
3284 3259 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3285 3260 min(8, ring_per_group);
3286 3261 }
3287 3262
3288 3263 break;
3289 3264
3290 3265 case ixgbe_mac_82599EB:
3291 3266 case ixgbe_mac_X540:
3292 3267 case ixgbe_mac_X550:
3293 3268 case ixgbe_mac_X550EM_x:
3294 3269 case ixgbe_mac_X550EM_a:
3295 3270 /*
3296 3271 * 82599 supports the following combination:
3297 3272 * vmdq no. x rss no.
3298 3273 * [33..64] x [1..2]
3299 3274 * [2..32] x [1..4]
3300 3275 * 1 x [1..16]
3301 3276 * However 8 rss queue per pool (vmdq) is sufficient for
3302 3277 * most cases.
3303 3278 *
3304 3279 * For now, treat X540 and X550 like the 82599.
3305 3280 */
3306 3281 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3307 3282 if (ixgbe->num_rx_groups == 1) {
3308 3283 ixgbe->num_rx_rings = min(8, ring_per_group);
3309 3284 } else if (ixgbe->num_rx_groups <= 32) {
3310 3285 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3311 3286 min(4, ring_per_group);
3312 3287 } else if (ixgbe->num_rx_groups <= 64) {
3313 3288 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3314 3289 min(2, ring_per_group);
3315 3290 }
3316 3291 break;
3317 3292
3318 3293 default:
3319 3294 break;
3320 3295 }
3321 3296
3322 3297 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3323 3298
3324 3299 if (ixgbe->num_rx_groups == 1 && ring_per_group == 1) {
3325 3300 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
3326 3301 } else if (ixgbe->num_rx_groups != 1 && ring_per_group == 1) {
3327 3302 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ;
3328 3303 } else if (ixgbe->num_rx_groups != 1 && ring_per_group != 1) {
3329 3304 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ_RSS;
3330 3305 } else {
3331 3306 ixgbe->classify_mode = IXGBE_CLASSIFY_RSS;
3332 3307 }
3333 3308
3334 3309 IXGBE_DEBUGLOG_2(ixgbe, "rx group number:%d, rx ring number:%d",
3335 3310 ixgbe->num_rx_groups, ixgbe->num_rx_rings);
3336 3311 }
3337 3312
3338 3313 /*
3339 3314 * ixgbe_get_conf - Get driver configurations set in driver.conf.
3340 3315 *
3341 3316 * This routine gets user-configured values out of the configuration
3342 3317 * file ixgbe.conf.
3343 3318 *
3344 3319 * For each configurable value, there is a minimum, a maximum, and a
3345 3320 * default.
3346 3321 * If user does not configure a value, use the default.
3347 3322 * If user configures below the minimum, use the minumum.
3348 3323 * If user configures above the maximum, use the maxumum.
3349 3324 */
3350 3325 static void
3351 3326 ixgbe_get_conf(ixgbe_t *ixgbe)
3352 3327 {
3353 3328 struct ixgbe_hw *hw = &ixgbe->hw;
3354 3329 uint32_t flow_control;
3355 3330
3356 3331 /*
3357 3332 * ixgbe driver supports the following user configurations:
3358 3333 *
3359 3334 * Jumbo frame configuration:
3360 3335 * default_mtu
3361 3336 *
3362 3337 * Ethernet flow control configuration:
3363 3338 * flow_control
3364 3339 *
3365 3340 * Multiple rings configurations:
3366 3341 * tx_queue_number
3367 3342 * tx_ring_size
3368 3343 * rx_queue_number
3369 3344 * rx_ring_size
3370 3345 *
3371 3346 * Call ixgbe_get_prop() to get the value for a specific
3372 3347 * configuration parameter.
3373 3348 */
3374 3349
3375 3350 /*
3376 3351 * Jumbo frame configuration - max_frame_size controls host buffer
3377 3352 * allocation, so includes MTU, ethernet header, vlan tag and
3378 3353 * frame check sequence.
3379 3354 */
3380 3355 ixgbe->default_mtu = ixgbe_get_prop(ixgbe, PROP_DEFAULT_MTU,
3381 3356 MIN_MTU, ixgbe->capab->max_mtu, DEFAULT_MTU);
3382 3357
3383 3358 ixgbe->max_frame_size = ixgbe->default_mtu +
3384 3359 sizeof (struct ether_vlan_header) + ETHERFCSL;
3385 3360
3386 3361 /*
3387 3362 * Ethernet flow control configuration
3388 3363 */
3389 3364 flow_control = ixgbe_get_prop(ixgbe, PROP_FLOW_CONTROL,
3390 3365 ixgbe_fc_none, 3, ixgbe_fc_none);
3391 3366 if (flow_control == 3)
3392 3367 flow_control = ixgbe_fc_default;
3393 3368
3394 3369 /*
3395 3370 * fc.requested mode is what the user requests. After autoneg,
3396 3371 * fc.current_mode will be the flow_control mode that was negotiated.
3397 3372 */
3398 3373 hw->fc.requested_mode = flow_control;
3399 3374
3400 3375 /*
3401 3376 * Multiple rings configurations
3402 3377 */
3403 3378 ixgbe->num_tx_rings = ixgbe_get_prop(ixgbe, PROP_TX_QUEUE_NUM,
3404 3379 ixgbe->capab->min_tx_que_num,
3405 3380 ixgbe->capab->max_tx_que_num,
3406 3381 ixgbe->capab->def_tx_que_num);
3407 3382 ixgbe->tx_ring_size = ixgbe_get_prop(ixgbe, PROP_TX_RING_SIZE,
3408 3383 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
3409 3384
3410 3385 ixgbe->num_rx_rings = ixgbe_get_prop(ixgbe, PROP_RX_QUEUE_NUM,
3411 3386 ixgbe->capab->min_rx_que_num,
3412 3387 ixgbe->capab->max_rx_que_num,
3413 3388 ixgbe->capab->def_rx_que_num);
3414 3389 ixgbe->rx_ring_size = ixgbe_get_prop(ixgbe, PROP_RX_RING_SIZE,
3415 3390 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
3416 3391
3417 3392 /*
3418 3393 * Multiple groups configuration
3419 3394 */
3420 3395 ixgbe->num_rx_groups = ixgbe_get_prop(ixgbe, PROP_RX_GROUP_NUM,
3421 3396 ixgbe->capab->min_rx_grp_num, ixgbe->capab->max_rx_grp_num,
3422 3397 ixgbe->capab->def_rx_grp_num);
3423 3398
3424 3399 ixgbe->mr_enable = ixgbe_get_prop(ixgbe, PROP_MR_ENABLE,
3425 3400 0, 1, DEFAULT_MR_ENABLE);
3426 3401
3427 3402 if (ixgbe->mr_enable == B_FALSE) {
3428 3403 ixgbe->num_tx_rings = 1;
3429 3404 ixgbe->num_rx_rings = 1;
3430 3405 ixgbe->num_rx_groups = 1;
3431 3406 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
3432 3407 } else {
3433 3408 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3434 3409 max(ixgbe->num_rx_rings / ixgbe->num_rx_groups, 1);
3435 3410 /*
3436 3411 * The combination of num_rx_rings and num_rx_groups
3437 3412 * may be not supported by h/w. We need to adjust
3438 3413 * them to appropriate values.
3439 3414 */
3440 3415 ixgbe_setup_vmdq_rss_conf(ixgbe);
3441 3416 }
3442 3417
3443 3418 /*
3444 3419 * Tunable used to force an interrupt type. The only use is
3445 3420 * for testing of the lesser interrupt types.
3446 3421 * 0 = don't force interrupt type
3447 3422 * 1 = force interrupt type MSI-X
3448 3423 * 2 = force interrupt type MSI
3449 3424 * 3 = force interrupt type Legacy
3450 3425 */
3451 3426 ixgbe->intr_force = ixgbe_get_prop(ixgbe, PROP_INTR_FORCE,
3452 3427 IXGBE_INTR_NONE, IXGBE_INTR_LEGACY, IXGBE_INTR_NONE);
3453 3428
3454 3429 ixgbe->tx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_TX_HCKSUM_ENABLE,
3455 3430 0, 1, DEFAULT_TX_HCKSUM_ENABLE);
3456 3431 ixgbe->rx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_RX_HCKSUM_ENABLE,
3457 3432 0, 1, DEFAULT_RX_HCKSUM_ENABLE);
3458 3433 ixgbe->lso_enable = ixgbe_get_prop(ixgbe, PROP_LSO_ENABLE,
3459 3434 0, 1, DEFAULT_LSO_ENABLE);
3460 3435 ixgbe->lro_enable = ixgbe_get_prop(ixgbe, PROP_LRO_ENABLE,
3461 3436 0, 1, DEFAULT_LRO_ENABLE);
3462 3437 ixgbe->tx_head_wb_enable = ixgbe_get_prop(ixgbe, PROP_TX_HEAD_WB_ENABLE,
3463 3438 0, 1, DEFAULT_TX_HEAD_WB_ENABLE);
3464 3439 ixgbe->relax_order_enable = ixgbe_get_prop(ixgbe,
3465 3440 PROP_RELAX_ORDER_ENABLE, 0, 1, DEFAULT_RELAX_ORDER_ENABLE);
3466 3441
3467 3442 /* Head Write Back not recommended for 82599, X540 and X550 */
3468 3443 if (hw->mac.type == ixgbe_mac_82599EB ||
3469 3444 hw->mac.type == ixgbe_mac_X540 ||
3470 3445 hw->mac.type == ixgbe_mac_X550 ||
3471 3446 hw->mac.type == ixgbe_mac_X550EM_x ||
3472 3447 hw->mac.type == ixgbe_mac_X550EM_a) {
3473 3448 ixgbe->tx_head_wb_enable = B_FALSE;
3474 3449 }
3475 3450
3476 3451 /*
3477 3452 * ixgbe LSO needs the tx h/w checksum support.
3478 3453 * LSO will be disabled if tx h/w checksum is not
3479 3454 * enabled.
3480 3455 */
3481 3456 if (ixgbe->tx_hcksum_enable == B_FALSE) {
3482 3457 ixgbe->lso_enable = B_FALSE;
3483 3458 }
3484 3459
3485 3460 /*
3486 3461 * ixgbe LRO needs the rx h/w checksum support.
3487 3462 * LRO will be disabled if rx h/w checksum is not
3488 3463 * enabled.
3489 3464 */
3490 3465 if (ixgbe->rx_hcksum_enable == B_FALSE) {
3491 3466 ixgbe->lro_enable = B_FALSE;
3492 3467 }
3493 3468
3494 3469 /*
3495 3470 * ixgbe LRO only supported by 82599, X540 and X550
3496 3471 */
3497 3472 if (hw->mac.type == ixgbe_mac_82598EB) {
3498 3473 ixgbe->lro_enable = B_FALSE;
3499 3474 }
3500 3475 ixgbe->tx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_TX_COPY_THRESHOLD,
3501 3476 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
3502 3477 DEFAULT_TX_COPY_THRESHOLD);
3503 3478 ixgbe->tx_recycle_thresh = ixgbe_get_prop(ixgbe,
3504 3479 PROP_TX_RECYCLE_THRESHOLD, MIN_TX_RECYCLE_THRESHOLD,
3505 3480 MAX_TX_RECYCLE_THRESHOLD, DEFAULT_TX_RECYCLE_THRESHOLD);
3506 3481 ixgbe->tx_overload_thresh = ixgbe_get_prop(ixgbe,
3507 3482 PROP_TX_OVERLOAD_THRESHOLD, MIN_TX_OVERLOAD_THRESHOLD,
3508 3483 MAX_TX_OVERLOAD_THRESHOLD, DEFAULT_TX_OVERLOAD_THRESHOLD);
3509 3484 ixgbe->tx_resched_thresh = ixgbe_get_prop(ixgbe,
3510 3485 PROP_TX_RESCHED_THRESHOLD, MIN_TX_RESCHED_THRESHOLD,
3511 3486 MAX_TX_RESCHED_THRESHOLD, DEFAULT_TX_RESCHED_THRESHOLD);
3512 3487
3513 3488 ixgbe->rx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_RX_COPY_THRESHOLD,
3514 3489 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
3515 3490 DEFAULT_RX_COPY_THRESHOLD);
3516 3491 ixgbe->rx_limit_per_intr = ixgbe_get_prop(ixgbe, PROP_RX_LIMIT_PER_INTR,
3517 3492 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
3518 3493 DEFAULT_RX_LIMIT_PER_INTR);
3519 3494
3520 3495 ixgbe->intr_throttling[0] = ixgbe_get_prop(ixgbe, PROP_INTR_THROTTLING,
3521 3496 ixgbe->capab->min_intr_throttle,
3522 3497 ixgbe->capab->max_intr_throttle,
3523 3498 ixgbe->capab->def_intr_throttle);
3524 3499 /*
3525 3500 * 82599, X540 and X550 require the interrupt throttling rate is
3526 3501 * a multiple of 8. This is enforced by the register definiton.
3527 3502 */
3528 3503 if (hw->mac.type == ixgbe_mac_82599EB ||
3529 3504 hw->mac.type == ixgbe_mac_X540 ||
3530 3505 hw->mac.type == ixgbe_mac_X550 ||
3531 3506 hw->mac.type == ixgbe_mac_X550EM_x ||
3532 3507 hw->mac.type == ixgbe_mac_X550EM_a)
3533 3508 ixgbe->intr_throttling[0] = ixgbe->intr_throttling[0] & 0xFF8;
3534 3509
3535 3510 hw->allow_unsupported_sfp = ixgbe_get_prop(ixgbe,
3536 3511 PROP_ALLOW_UNSUPPORTED_SFP, 0, 1, DEFAULT_ALLOW_UNSUPPORTED_SFP);
3537 3512 }
3538 3513
3539 3514 static void
3540 3515 ixgbe_init_params(ixgbe_t *ixgbe)
3541 3516 {
3542 3517 struct ixgbe_hw *hw = &ixgbe->hw;
3543 3518 ixgbe_link_speed speeds_supported = 0;
3544 3519 boolean_t negotiate;
3545 3520
3546 3521 /*
3547 3522 * Get a list of speeds the adapter supports. If the hw struct hasn't
3548 3523 * been populated with this information yet, retrieve it from the
3549 3524 * adapter and save it to our own variable.
3550 3525 *
3551 3526 * On certain adapters, such as ones which use SFPs, the contents of
3552 3527 * hw->phy.speeds_supported (and hw->phy.autoneg_advertised) are not
3553 3528 * updated, so we must rely on calling ixgbe_get_link_capabilities()
3554 3529 * in order to ascertain the speeds which we are capable of supporting,
3555 3530 * and in the case of SFP-equipped adapters, which speed we are
3556 3531 * advertising. If ixgbe_get_link_capabilities() fails for some reason,
3557 3532 * we'll go with a default list of speeds as a last resort.
3558 3533 */
3559 3534 speeds_supported = hw->phy.speeds_supported;
3560 3535
3561 3536 if (speeds_supported == 0) {
3562 3537 if (ixgbe_get_link_capabilities(hw, &speeds_supported,
3563 3538 &negotiate) != IXGBE_SUCCESS) {
3564 3539 if (hw->mac.type == ixgbe_mac_82598EB) {
3565 3540 speeds_supported =
3566 3541 IXGBE_LINK_SPEED_82598_AUTONEG;
3567 3542 } else {
3568 3543 speeds_supported =
3569 3544 IXGBE_LINK_SPEED_82599_AUTONEG;
3570 3545 }
3571 3546 }
3572 3547 }
3573 3548 ixgbe->speeds_supported = speeds_supported;
3574 3549
3575 3550 /*
3576 3551 * By default, all supported speeds are enabled and advertised.
3577 3552 */
3578 3553 if (speeds_supported & IXGBE_LINK_SPEED_10GB_FULL) {
3579 3554 ixgbe->param_en_10000fdx_cap = 1;
3580 3555 ixgbe->param_adv_10000fdx_cap = 1;
3581 3556 } else {
3582 3557 ixgbe->param_en_10000fdx_cap = 0;
3583 3558 ixgbe->param_adv_10000fdx_cap = 0;
3584 3559 }
3585 3560
3586 3561 if (speeds_supported & IXGBE_LINK_SPEED_5GB_FULL) {
3587 3562 ixgbe->param_en_5000fdx_cap = 1;
3588 3563 ixgbe->param_adv_5000fdx_cap = 1;
3589 3564 } else {
3590 3565 ixgbe->param_en_5000fdx_cap = 0;
3591 3566 ixgbe->param_adv_5000fdx_cap = 0;
3592 3567 }
3593 3568
3594 3569 if (speeds_supported & IXGBE_LINK_SPEED_2_5GB_FULL) {
3595 3570 ixgbe->param_en_2500fdx_cap = 1;
3596 3571 ixgbe->param_adv_2500fdx_cap = 1;
3597 3572 } else {
3598 3573 ixgbe->param_en_2500fdx_cap = 0;
3599 3574 ixgbe->param_adv_2500fdx_cap = 0;
3600 3575 }
3601 3576
3602 3577 if (speeds_supported & IXGBE_LINK_SPEED_1GB_FULL) {
3603 3578 ixgbe->param_en_1000fdx_cap = 1;
3604 3579 ixgbe->param_adv_1000fdx_cap = 1;
3605 3580 } else {
3606 3581 ixgbe->param_en_1000fdx_cap = 0;
3607 3582 ixgbe->param_adv_1000fdx_cap = 0;
3608 3583 }
3609 3584
3610 3585 if (speeds_supported & IXGBE_LINK_SPEED_100_FULL) {
3611 3586 ixgbe->param_en_100fdx_cap = 1;
3612 3587 ixgbe->param_adv_100fdx_cap = 1;
3613 3588 } else {
3614 3589 ixgbe->param_en_100fdx_cap = 0;
3615 3590 ixgbe->param_adv_100fdx_cap = 0;
3616 3591 }
3617 3592
3618 3593 ixgbe->param_pause_cap = 1;
3619 3594 ixgbe->param_asym_pause_cap = 1;
3620 3595 ixgbe->param_rem_fault = 0;
3621 3596
3622 3597 ixgbe->param_adv_autoneg_cap = 1;
3623 3598 ixgbe->param_adv_pause_cap = 1;
3624 3599 ixgbe->param_adv_asym_pause_cap = 1;
3625 3600 ixgbe->param_adv_rem_fault = 0;
3626 3601
3627 3602 ixgbe->param_lp_10000fdx_cap = 0;
3628 3603 ixgbe->param_lp_5000fdx_cap = 0;
3629 3604 ixgbe->param_lp_2500fdx_cap = 0;
3630 3605 ixgbe->param_lp_1000fdx_cap = 0;
3631 3606 ixgbe->param_lp_100fdx_cap = 0;
3632 3607 ixgbe->param_lp_autoneg_cap = 0;
3633 3608 ixgbe->param_lp_pause_cap = 0;
3634 3609 ixgbe->param_lp_asym_pause_cap = 0;
3635 3610 ixgbe->param_lp_rem_fault = 0;
3636 3611 }
3637 3612
3638 3613 /*
3639 3614 * ixgbe_get_prop - Get a property value out of the configuration file
3640 3615 * ixgbe.conf.
3641 3616 *
3642 3617 * Caller provides the name of the property, a default value, a minimum
3643 3618 * value, and a maximum value.
3644 3619 *
3645 3620 * Return configured value of the property, with default, minimum and
3646 3621 * maximum properly applied.
3647 3622 */
3648 3623 static int
3649 3624 ixgbe_get_prop(ixgbe_t *ixgbe,
3650 3625 char *propname, /* name of the property */
3651 3626 int minval, /* minimum acceptable value */
3652 3627 int maxval, /* maximim acceptable value */
3653 3628 int defval) /* default value */
3654 3629 {
3655 3630 int value;
3656 3631
3657 3632 /*
3658 3633 * Call ddi_prop_get_int() to read the conf settings
3659 3634 */
3660 3635 value = ddi_prop_get_int(DDI_DEV_T_ANY, ixgbe->dip,
3661 3636 DDI_PROP_DONTPASS, propname, defval);
3662 3637 if (value > maxval)
3663 3638 value = maxval;
3664 3639
3665 3640 if (value < minval)
3666 3641 value = minval;
3667 3642
3668 3643 return (value);
3669 3644 }
3670 3645
3671 3646 /*
3672 3647 * ixgbe_driver_setup_link - Using the link properties to setup the link.
3673 3648 */
3674 3649 int
3675 3650 ixgbe_driver_setup_link(ixgbe_t *ixgbe, boolean_t setup_hw)
3676 3651 {
3677 3652 struct ixgbe_hw *hw = &ixgbe->hw;
3678 3653 ixgbe_link_speed advertised = 0;
3679 3654
3680 3655 /*
3681 3656 * Assemble a list of enabled speeds to auto-negotiate with.
3682 3657 */
3683 3658 if (ixgbe->param_en_10000fdx_cap == 1)
3684 3659 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
3685 3660
3686 3661 if (ixgbe->param_en_5000fdx_cap == 1)
3687 3662 advertised |= IXGBE_LINK_SPEED_5GB_FULL;
3688 3663
3689 3664 if (ixgbe->param_en_2500fdx_cap == 1)
3690 3665 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
3691 3666
3692 3667 if (ixgbe->param_en_1000fdx_cap == 1)
3693 3668 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
3694 3669
3695 3670 if (ixgbe->param_en_100fdx_cap == 1)
3696 3671 advertised |= IXGBE_LINK_SPEED_100_FULL;
3697 3672
3698 3673 /*
3699 3674 * As a last resort, autoneg with a default list of speeds.
3700 3675 */
3701 3676 if (ixgbe->param_adv_autoneg_cap == 1 && advertised == 0) {
3702 3677 ixgbe_notice(ixgbe, "Invalid link settings. Setting link "
3703 3678 "to autonegotiate with full capabilities.");
3704 3679
3705 3680 if (hw->mac.type == ixgbe_mac_82598EB)
3706 3681 advertised = IXGBE_LINK_SPEED_82598_AUTONEG;
3707 3682 else
3708 3683 advertised = IXGBE_LINK_SPEED_82599_AUTONEG;
3709 3684 }
3710 3685
3711 3686 if (setup_hw) {
3712 3687 if (ixgbe_setup_link(&ixgbe->hw, advertised,
3713 3688 ixgbe->param_adv_autoneg_cap) != IXGBE_SUCCESS) {
3714 3689 ixgbe_notice(ixgbe, "Setup link failed on this "
3715 3690 "device.");
3716 3691 return (IXGBE_FAILURE);
3717 3692 }
3718 3693 }
3719 3694
3720 3695 return (IXGBE_SUCCESS);
3721 3696 }
3722 3697
3723 3698 /*
3724 3699 * ixgbe_driver_link_check - Link status processing.
3725 3700 *
3726 3701 * This function can be called in both kernel context and interrupt context
3727 3702 */
3728 3703 static void
3729 3704 ixgbe_driver_link_check(ixgbe_t *ixgbe)
3730 3705 {
3731 3706 struct ixgbe_hw *hw = &ixgbe->hw;
3732 3707 ixgbe_link_speed speed = IXGBE_LINK_SPEED_UNKNOWN;
3733 3708 boolean_t link_up = B_FALSE;
3734 3709 boolean_t link_changed = B_FALSE;
3735 3710
3736 3711 ASSERT(mutex_owned(&ixgbe->gen_lock));
3737 3712
3738 3713 (void) ixgbe_check_link(hw, &speed, &link_up, B_FALSE);
3739 3714 if (link_up) {
3740 3715 ixgbe->link_check_complete = B_TRUE;
3741 3716
3742 3717 /* Link is up, enable flow control settings */
3743 3718 (void) ixgbe_fc_enable(hw);
3744 3719
3745 3720 /*
3746 3721 * The Link is up, check whether it was marked as down earlier
3747 3722 */
3748 3723 if (ixgbe->link_state != LINK_STATE_UP) {
3749 3724 switch (speed) {
3750 3725 case IXGBE_LINK_SPEED_10GB_FULL:
3751 3726 ixgbe->link_speed = SPEED_10GB;
3752 3727 break;
3753 3728 case IXGBE_LINK_SPEED_5GB_FULL:
3754 3729 ixgbe->link_speed = SPEED_5GB;
3755 3730 break;
3756 3731 case IXGBE_LINK_SPEED_2_5GB_FULL:
3757 3732 ixgbe->link_speed = SPEED_2_5GB;
3758 3733 break;
3759 3734 case IXGBE_LINK_SPEED_1GB_FULL:
3760 3735 ixgbe->link_speed = SPEED_1GB;
3761 3736 break;
3762 3737 case IXGBE_LINK_SPEED_100_FULL:
3763 3738 ixgbe->link_speed = SPEED_100;
3764 3739 }
3765 3740 ixgbe->link_duplex = LINK_DUPLEX_FULL;
3766 3741 ixgbe->link_state = LINK_STATE_UP;
3767 3742 link_changed = B_TRUE;
3768 3743 }
3769 3744 } else {
3770 3745 if (ixgbe->link_check_complete == B_TRUE ||
3771 3746 (ixgbe->link_check_complete == B_FALSE &&
3772 3747 gethrtime() >= ixgbe->link_check_hrtime)) {
3773 3748 /*
3774 3749 * The link is really down
3775 3750 */
3776 3751 ixgbe->link_check_complete = B_TRUE;
3777 3752
3778 3753 if (ixgbe->link_state != LINK_STATE_DOWN) {
3779 3754 ixgbe->link_speed = 0;
3780 3755 ixgbe->link_duplex = LINK_DUPLEX_UNKNOWN;
3781 3756 ixgbe->link_state = LINK_STATE_DOWN;
3782 3757 link_changed = B_TRUE;
3783 3758 }
3784 3759 }
3785 3760 }
3786 3761
3787 3762 /*
3788 3763 * If we are in an interrupt context, need to re-enable the
3789 3764 * interrupt, which was automasked
3790 3765 */
3791 3766 if (servicing_interrupt() != 0) {
3792 3767 ixgbe->eims |= IXGBE_EICR_LSC;
3793 3768 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
3794 3769 }
3795 3770
3796 3771 if (link_changed) {
3797 3772 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
3798 3773 }
3799 3774 }
3800 3775
3801 3776 /*
3802 3777 * ixgbe_sfp_check - sfp module processing done in taskq only for 82599.
3803 3778 */
3804 3779 static void
3805 3780 ixgbe_sfp_check(void *arg)
3806 3781 {
3807 3782 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3808 3783 uint32_t eicr = ixgbe->eicr;
3809 3784 struct ixgbe_hw *hw = &ixgbe->hw;
3810 3785
3811 3786 mutex_enter(&ixgbe->gen_lock);
3812 3787 (void) hw->phy.ops.identify_sfp(hw);
3813 3788 if (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw)) {
3814 3789 /* clear the interrupt */
3815 3790 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
3816 3791
3817 3792 /* if link up, do multispeed fiber setup */
3818 3793 (void) ixgbe_setup_link(hw, IXGBE_LINK_SPEED_82599_AUTONEG,
3819 3794 B_TRUE);
3820 3795 ixgbe_driver_link_check(ixgbe);
3821 3796 ixgbe_get_hw_state(ixgbe);
3822 3797 } else if (eicr & IXGBE_EICR_GPI_SDP2_BY_MAC(hw)) {
3823 3798 /* clear the interrupt */
3824 3799 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2_BY_MAC(hw));
3825 3800
3826 3801 /* if link up, do sfp module setup */
3827 3802 (void) hw->mac.ops.setup_sfp(hw);
3828 3803
3829 3804 /* do multispeed fiber setup */
3830 3805 (void) ixgbe_setup_link(hw, IXGBE_LINK_SPEED_82599_AUTONEG,
3831 3806 B_TRUE);
3832 3807 ixgbe_driver_link_check(ixgbe);
3833 3808 ixgbe_get_hw_state(ixgbe);
3834 3809 }
3835 3810 mutex_exit(&ixgbe->gen_lock);
3836 3811
3837 3812 /*
3838 3813 * We need to fully re-check the link later.
3839 3814 */
3840 3815 ixgbe->link_check_complete = B_FALSE;
3841 3816 ixgbe->link_check_hrtime = gethrtime() +
3842 3817 (IXGBE_LINK_UP_TIME * 100000000ULL);
3843 3818 }
3844 3819
3845 3820 /*
3846 3821 * ixgbe_overtemp_check - overtemp module processing done in taskq
3847 3822 *
3848 3823 * This routine will only be called on adapters with temperature sensor.
3849 3824 * The indication of over-temperature can be either SDP0 interrupt or the link
3850 3825 * status change interrupt.
3851 3826 */
3852 3827 static void
3853 3828 ixgbe_overtemp_check(void *arg)
3854 3829 {
3855 3830 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3856 3831 struct ixgbe_hw *hw = &ixgbe->hw;
3857 3832 uint32_t eicr = ixgbe->eicr;
3858 3833 ixgbe_link_speed speed;
3859 3834 boolean_t link_up;
3860 3835
3861 3836 mutex_enter(&ixgbe->gen_lock);
3862 3837
3863 3838 /* make sure we know current state of link */
3864 3839 (void) ixgbe_check_link(hw, &speed, &link_up, B_FALSE);
3865 3840
3866 3841 /* check over-temp condition */
3867 3842 if (((eicr & IXGBE_EICR_GPI_SDP0_BY_MAC(hw)) && (!link_up)) ||
3868 3843 (eicr & IXGBE_EICR_LSC)) {
3869 3844 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) {
3870 3845 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
3871 3846
3872 3847 /*
3873 3848 * Disable the adapter interrupts
3874 3849 */
3875 3850 ixgbe_disable_adapter_interrupts(ixgbe);
3876 3851
3877 3852 /*
3878 3853 * Disable Rx/Tx units
3879 3854 */
3880 3855 (void) ixgbe_stop_adapter(hw);
3881 3856
3882 3857 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
3883 3858 ixgbe_error(ixgbe,
3884 3859 "Problem: Network adapter has been stopped "
3885 3860 "because it has overheated");
3886 3861 ixgbe_error(ixgbe,
3887 3862 "Action: Restart the computer. "
3888 3863 "If the problem persists, power off the system "
3889 3864 "and replace the adapter");
3890 3865 }
3891 3866 }
3892 3867
3893 3868 /* write to clear the interrupt */
3894 3869 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3895 3870
3896 3871 mutex_exit(&ixgbe->gen_lock);
3897 3872 }
3898 3873
3899 3874 /*
3900 3875 * ixgbe_phy_check - taskq to process interrupts from an external PHY
3901 3876 *
3902 3877 * This routine will only be called on adapters with external PHYs
3903 3878 * (such as X550) that may be trying to raise our attention to some event.
3904 3879 * Currently, this is limited to claiming PHY overtemperature and link status
3905 3880 * change (LSC) events, however this may expand to include other things in
3906 3881 * future adapters.
3907 3882 */
3908 3883 static void
3909 3884 ixgbe_phy_check(void *arg)
3910 3885 {
3911 3886 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3912 3887 struct ixgbe_hw *hw = &ixgbe->hw;
3913 3888 int rv;
3914 3889
3915 3890 mutex_enter(&ixgbe->gen_lock);
3916 3891
3917 3892 /*
3918 3893 * X550 baseT PHY overtemp and LSC events are handled here.
3919 3894 *
3920 3895 * If an overtemp event occurs, it will be reflected in the
3921 3896 * return value of phy.ops.handle_lasi() and the common code will
3922 3897 * automatically power off the baseT PHY. This is our cue to trigger
3923 3898 * an FMA event.
3924 3899 *
3925 3900 * If a link status change event occurs, phy.ops.handle_lasi() will
3926 3901 * automatically initiate a link setup between the integrated KR PHY
3927 3902 * and the external X557 PHY to ensure that the link speed between
3928 3903 * them matches the link speed of the baseT link.
3929 3904 */
3930 3905 rv = ixgbe_handle_lasi(hw);
3931 3906
3932 3907 if (rv == IXGBE_ERR_OVERTEMP) {
3933 3908 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
3934 3909
3935 3910 /*
3936 3911 * Disable the adapter interrupts
3937 3912 */
3938 3913 ixgbe_disable_adapter_interrupts(ixgbe);
3939 3914
3940 3915 /*
3941 3916 * Disable Rx/Tx units
3942 3917 */
3943 3918 (void) ixgbe_stop_adapter(hw);
3944 3919
3945 3920 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
3946 3921 ixgbe_error(ixgbe,
3947 3922 "Problem: Network adapter has been stopped due to a "
3948 3923 "overtemperature event being detected.");
3949 3924 ixgbe_error(ixgbe,
3950 3925 "Action: Shut down or restart the computer. If the issue "
3951 3926 "persists, please take action in accordance with the "
3952 3927 "recommendations from your system vendor.");
3953 3928 }
3954 3929
3955 3930 mutex_exit(&ixgbe->gen_lock);
3956 3931 }
3957 3932
3958 3933 /*
3959 3934 * ixgbe_link_timer - timer for link status detection
3960 3935 */
3961 3936 static void
3962 3937 ixgbe_link_timer(void *arg)
3963 3938 {
3964 3939 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3965 3940
3966 3941 mutex_enter(&ixgbe->gen_lock);
3967 3942 ixgbe_driver_link_check(ixgbe);
3968 3943 mutex_exit(&ixgbe->gen_lock);
3969 3944 }
3970 3945
3971 3946 /*
3972 3947 * ixgbe_local_timer - Driver watchdog function.
3973 3948 *
3974 3949 * This function will handle the transmit stall check and other routines.
3975 3950 */
3976 3951 static void
3977 3952 ixgbe_local_timer(void *arg)
3978 3953 {
3979 3954 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3980 3955
3981 3956 if (ixgbe->ixgbe_state & IXGBE_OVERTEMP)
3982 3957 goto out;
3983 3958
3984 3959 if (ixgbe->ixgbe_state & IXGBE_ERROR) {
3985 3960 ixgbe->reset_count++;
3986 3961 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3987 3962 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3988 3963 goto out;
3989 3964 }
3990 3965
3991 3966 if (ixgbe_stall_check(ixgbe)) {
3992 3967 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STALL);
3993 3968 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3994 3969
3995 3970 ixgbe->reset_count++;
3996 3971 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3997 3972 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3998 3973 }
3999 3974
4000 3975 out:
4001 3976 ixgbe_restart_watchdog_timer(ixgbe);
4002 3977 }
4003 3978
4004 3979 /*
4005 3980 * ixgbe_stall_check - Check for transmit stall.
4006 3981 *
4007 3982 * This function checks if the adapter is stalled (in transmit).
4008 3983 *
4009 3984 * It is called each time the watchdog timeout is invoked.
4010 3985 * If the transmit descriptor reclaim continuously fails,
4011 3986 * the watchdog value will increment by 1. If the watchdog
4012 3987 * value exceeds the threshold, the ixgbe is assumed to
4013 3988 * have stalled and need to be reset.
4014 3989 */
4015 3990 static boolean_t
4016 3991 ixgbe_stall_check(ixgbe_t *ixgbe)
4017 3992 {
4018 3993 ixgbe_tx_ring_t *tx_ring;
4019 3994 boolean_t result;
4020 3995 int i;
4021 3996
4022 3997 if (ixgbe->link_state != LINK_STATE_UP)
4023 3998 return (B_FALSE);
4024 3999
4025 4000 /*
4026 4001 * If any tx ring is stalled, we'll reset the chipset
4027 4002 */
4028 4003 result = B_FALSE;
4029 4004 for (i = 0; i < ixgbe->num_tx_rings; i++) {
4030 4005 tx_ring = &ixgbe->tx_rings[i];
4031 4006 if (tx_ring->tbd_free <= ixgbe->tx_recycle_thresh) {
4032 4007 tx_ring->tx_recycle(tx_ring);
4033 4008 }
4034 4009
4035 4010 if (tx_ring->recycle_fail > 0)
4036 4011 tx_ring->stall_watchdog++;
4037 4012 else
4038 4013 tx_ring->stall_watchdog = 0;
4039 4014
4040 4015 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
4041 4016 result = B_TRUE;
4042 4017 break;
4043 4018 }
4044 4019 }
4045 4020
4046 4021 if (result) {
4047 4022 tx_ring->stall_watchdog = 0;
4048 4023 tx_ring->recycle_fail = 0;
4049 4024 }
4050 4025
4051 4026 return (result);
4052 4027 }
4053 4028
4054 4029
4055 4030 /*
4056 4031 * is_valid_mac_addr - Check if the mac address is valid.
4057 4032 */
4058 4033 static boolean_t
4059 4034 is_valid_mac_addr(uint8_t *mac_addr)
4060 4035 {
4061 4036 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
4062 4037 const uint8_t addr_test2[6] =
4063 4038 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
4064 4039
4065 4040 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
4066 4041 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
4067 4042 return (B_FALSE);
4068 4043
4069 4044 return (B_TRUE);
4070 4045 }
4071 4046
4072 4047 static boolean_t
4073 4048 ixgbe_find_mac_address(ixgbe_t *ixgbe)
4074 4049 {
4075 4050 #ifdef __sparc
4076 4051 struct ixgbe_hw *hw = &ixgbe->hw;
4077 4052 uchar_t *bytes;
4078 4053 struct ether_addr sysaddr;
4079 4054 uint_t nelts;
4080 4055 int err;
4081 4056 boolean_t found = B_FALSE;
4082 4057
4083 4058 /*
4084 4059 * The "vendor's factory-set address" may already have
4085 4060 * been extracted from the chip, but if the property
4086 4061 * "local-mac-address" is set we use that instead.
4087 4062 *
4088 4063 * We check whether it looks like an array of 6
4089 4064 * bytes (which it should, if OBP set it). If we can't
4090 4065 * make sense of it this way, we'll ignore it.
4091 4066 */
4092 4067 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
4093 4068 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
4094 4069 if (err == DDI_PROP_SUCCESS) {
4095 4070 if (nelts == ETHERADDRL) {
4096 4071 while (nelts--)
4097 4072 hw->mac.addr[nelts] = bytes[nelts];
4098 4073 found = B_TRUE;
4099 4074 }
4100 4075 ddi_prop_free(bytes);
4101 4076 }
4102 4077
4103 4078 /*
4104 4079 * Look up the OBP property "local-mac-address?". If the user has set
4105 4080 * 'local-mac-address? = false', use "the system address" instead.
4106 4081 */
4107 4082 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 0,
4108 4083 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
4109 4084 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
4110 4085 if (localetheraddr(NULL, &sysaddr) != 0) {
4111 4086 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
4112 4087 found = B_TRUE;
4113 4088 }
4114 4089 }
4115 4090 ddi_prop_free(bytes);
4116 4091 }
4117 4092
4118 4093 /*
4119 4094 * Finally(!), if there's a valid "mac-address" property (created
4120 4095 * if we netbooted from this interface), we must use this instead
4121 4096 * of any of the above to ensure that the NFS/install server doesn't
4122 4097 * get confused by the address changing as illumos takes over!
4123 4098 */
4124 4099 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
4125 4100 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
4126 4101 if (err == DDI_PROP_SUCCESS) {
4127 4102 if (nelts == ETHERADDRL) {
4128 4103 while (nelts--)
4129 4104 hw->mac.addr[nelts] = bytes[nelts];
4130 4105 found = B_TRUE;
4131 4106 }
4132 4107 ddi_prop_free(bytes);
4133 4108 }
4134 4109
4135 4110 if (found) {
4136 4111 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
4137 4112 return (B_TRUE);
4138 4113 }
4139 4114 #else
4140 4115 _NOTE(ARGUNUSED(ixgbe));
4141 4116 #endif
4142 4117
4143 4118 return (B_TRUE);
4144 4119 }
4145 4120
4146 4121 #pragma inline(ixgbe_arm_watchdog_timer)
4147 4122 static void
4148 4123 ixgbe_arm_watchdog_timer(ixgbe_t *ixgbe)
4149 4124 {
4150 4125 /*
4151 4126 * Fire a watchdog timer
4152 4127 */
4153 4128 ixgbe->watchdog_tid =
4154 4129 timeout(ixgbe_local_timer,
4155 4130 (void *)ixgbe, 1 * drv_usectohz(1000000));
4156 4131
4157 4132 }
4158 4133
4159 4134 /*
4160 4135 * ixgbe_enable_watchdog_timer - Enable and start the driver watchdog timer.
4161 4136 */
4162 4137 void
4163 4138 ixgbe_enable_watchdog_timer(ixgbe_t *ixgbe)
4164 4139 {
4165 4140 mutex_enter(&ixgbe->watchdog_lock);
4166 4141
4167 4142 if (!ixgbe->watchdog_enable) {
4168 4143 ixgbe->watchdog_enable = B_TRUE;
4169 4144 ixgbe->watchdog_start = B_TRUE;
4170 4145 ixgbe_arm_watchdog_timer(ixgbe);
4171 4146 }
4172 4147
4173 4148 mutex_exit(&ixgbe->watchdog_lock);
4174 4149 }
4175 4150
4176 4151 /*
4177 4152 * ixgbe_disable_watchdog_timer - Disable and stop the driver watchdog timer.
4178 4153 */
4179 4154 void
4180 4155 ixgbe_disable_watchdog_timer(ixgbe_t *ixgbe)
4181 4156 {
4182 4157 timeout_id_t tid;
4183 4158
4184 4159 mutex_enter(&ixgbe->watchdog_lock);
4185 4160
4186 4161 ixgbe->watchdog_enable = B_FALSE;
4187 4162 ixgbe->watchdog_start = B_FALSE;
4188 4163 tid = ixgbe->watchdog_tid;
4189 4164 ixgbe->watchdog_tid = 0;
4190 4165
4191 4166 mutex_exit(&ixgbe->watchdog_lock);
4192 4167
4193 4168 if (tid != 0)
4194 4169 (void) untimeout(tid);
4195 4170 }
4196 4171
4197 4172 /*
4198 4173 * ixgbe_start_watchdog_timer - Start the driver watchdog timer.
4199 4174 */
4200 4175 void
4201 4176 ixgbe_start_watchdog_timer(ixgbe_t *ixgbe)
4202 4177 {
4203 4178 mutex_enter(&ixgbe->watchdog_lock);
4204 4179
4205 4180 if (ixgbe->watchdog_enable) {
4206 4181 if (!ixgbe->watchdog_start) {
4207 4182 ixgbe->watchdog_start = B_TRUE;
4208 4183 ixgbe_arm_watchdog_timer(ixgbe);
4209 4184 }
4210 4185 }
4211 4186
4212 4187 mutex_exit(&ixgbe->watchdog_lock);
4213 4188 }
4214 4189
4215 4190 /*
4216 4191 * ixgbe_restart_watchdog_timer - Restart the driver watchdog timer.
4217 4192 */
4218 4193 static void
4219 4194 ixgbe_restart_watchdog_timer(ixgbe_t *ixgbe)
4220 4195 {
4221 4196 mutex_enter(&ixgbe->watchdog_lock);
4222 4197
4223 4198 if (ixgbe->watchdog_start)
4224 4199 ixgbe_arm_watchdog_timer(ixgbe);
4225 4200
4226 4201 mutex_exit(&ixgbe->watchdog_lock);
4227 4202 }
4228 4203
4229 4204 /*
4230 4205 * ixgbe_stop_watchdog_timer - Stop the driver watchdog timer.
4231 4206 */
4232 4207 void
4233 4208 ixgbe_stop_watchdog_timer(ixgbe_t *ixgbe)
4234 4209 {
4235 4210 timeout_id_t tid;
4236 4211
4237 4212 mutex_enter(&ixgbe->watchdog_lock);
4238 4213
4239 4214 ixgbe->watchdog_start = B_FALSE;
4240 4215 tid = ixgbe->watchdog_tid;
4241 4216 ixgbe->watchdog_tid = 0;
4242 4217
4243 4218 mutex_exit(&ixgbe->watchdog_lock);
4244 4219
4245 4220 if (tid != 0)
4246 4221 (void) untimeout(tid);
4247 4222 }
4248 4223
4249 4224 /*
4250 4225 * ixgbe_disable_adapter_interrupts - Disable all adapter interrupts.
4251 4226 */
4252 4227 static void
4253 4228 ixgbe_disable_adapter_interrupts(ixgbe_t *ixgbe)
4254 4229 {
4255 4230 struct ixgbe_hw *hw = &ixgbe->hw;
4256 4231
4257 4232 /*
4258 4233 * mask all interrupts off
4259 4234 */
4260 4235 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xffffffff);
4261 4236
4262 4237 /*
4263 4238 * for MSI-X, also disable autoclear
4264 4239 */
4265 4240 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
4266 4241 IXGBE_WRITE_REG(hw, IXGBE_EIAC, 0x0);
4267 4242 }
4268 4243
4269 4244 IXGBE_WRITE_FLUSH(hw);
4270 4245 }
4271 4246
4272 4247 /*
4273 4248 * ixgbe_enable_adapter_interrupts - Enable all hardware interrupts.
4274 4249 */
4275 4250 static void
4276 4251 ixgbe_enable_adapter_interrupts(ixgbe_t *ixgbe)
4277 4252 {
4278 4253 struct ixgbe_hw *hw = &ixgbe->hw;
4279 4254 uint32_t eiac, eiam;
4280 4255 uint32_t gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4281 4256
4282 4257 /* interrupt types to enable */
4283 4258 ixgbe->eims = IXGBE_EIMS_ENABLE_MASK; /* shared code default */
4284 4259 ixgbe->eims &= ~IXGBE_EIMS_TCP_TIMER; /* minus tcp timer */
4285 4260 ixgbe->eims |= ixgbe->capab->other_intr; /* "other" interrupt types */
4286 4261
4287 4262 /* enable automask on "other" causes that this adapter can generate */
4288 4263 eiam = ixgbe->capab->other_intr;
4289 4264
4290 4265 /*
4291 4266 * msi-x mode
4292 4267 */
4293 4268 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
4294 4269 /* enable autoclear but not on bits 29:20 */
4295 4270 eiac = (ixgbe->eims & ~IXGBE_OTHER_INTR);
4296 4271
4297 4272 /* general purpose interrupt enable */
4298 4273 gpie |= (IXGBE_GPIE_MSIX_MODE
4299 4274 | IXGBE_GPIE_PBA_SUPPORT
4300 4275 | IXGBE_GPIE_OCD
4301 4276 | IXGBE_GPIE_EIAME);
4302 4277 /*
4303 4278 * non-msi-x mode
4304 4279 */
4305 4280 } else {
4306 4281
4307 4282 /* disable autoclear, leave gpie at default */
4308 4283 eiac = 0;
4309 4284
4310 4285 /*
4311 4286 * General purpose interrupt enable.
4312 4287 * For 82599, X540 and X550, extended interrupt
4313 4288 * automask enable only in MSI or MSI-X mode
4314 4289 */
4315 4290 if ((hw->mac.type == ixgbe_mac_82598EB) ||
4316 4291 (ixgbe->intr_type == DDI_INTR_TYPE_MSI)) {
4317 4292 gpie |= IXGBE_GPIE_EIAME;
4318 4293 }
4319 4294 }
4320 4295
4321 4296 /* Enable specific "other" interrupt types */
4322 4297 switch (hw->mac.type) {
4323 4298 case ixgbe_mac_82598EB:
4324 4299 gpie |= ixgbe->capab->other_gpie;
4325 4300 break;
4326 4301
4327 4302 case ixgbe_mac_82599EB:
4328 4303 case ixgbe_mac_X540:
4329 4304 case ixgbe_mac_X550:
4330 4305 case ixgbe_mac_X550EM_x:
4331 4306 case ixgbe_mac_X550EM_a:
4332 4307 gpie |= ixgbe->capab->other_gpie;
4333 4308
4334 4309 /* Enable RSC Delay 8us when LRO enabled */
4335 4310 if (ixgbe->lro_enable) {
4336 4311 gpie |= (1 << IXGBE_GPIE_RSC_DELAY_SHIFT);
4337 4312 }
4338 4313 break;
4339 4314
4340 4315 default:
4341 4316 break;
4342 4317 }
4343 4318
4344 4319 /* write to interrupt control registers */
4345 4320 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4346 4321 IXGBE_WRITE_REG(hw, IXGBE_EIAC, eiac);
4347 4322 IXGBE_WRITE_REG(hw, IXGBE_EIAM, eiam);
4348 4323 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4349 4324 IXGBE_WRITE_FLUSH(hw);
4350 4325 }
4351 4326
4352 4327 /*
4353 4328 * ixgbe_loopback_ioctl - Loopback support.
4354 4329 */
4355 4330 enum ioc_reply
4356 4331 ixgbe_loopback_ioctl(ixgbe_t *ixgbe, struct iocblk *iocp, mblk_t *mp)
4357 4332 {
4358 4333 lb_info_sz_t *lbsp;
4359 4334 lb_property_t *lbpp;
4360 4335 uint32_t *lbmp;
4361 4336 uint32_t size;
4362 4337 uint32_t value;
4363 4338
4364 4339 if (mp->b_cont == NULL)
4365 4340 return (IOC_INVAL);
4366 4341
4367 4342 switch (iocp->ioc_cmd) {
4368 4343 default:
4369 4344 return (IOC_INVAL);
4370 4345
4371 4346 case LB_GET_INFO_SIZE:
4372 4347 size = sizeof (lb_info_sz_t);
4373 4348 if (iocp->ioc_count != size)
4374 4349 return (IOC_INVAL);
4375 4350
4376 4351 value = sizeof (lb_normal);
4377 4352 value += sizeof (lb_mac);
4378 4353 value += sizeof (lb_external);
4379 4354
4380 4355 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
4381 4356 *lbsp = value;
4382 4357 break;
4383 4358
4384 4359 case LB_GET_INFO:
4385 4360 value = sizeof (lb_normal);
4386 4361 value += sizeof (lb_mac);
4387 4362 value += sizeof (lb_external);
4388 4363
4389 4364 size = value;
4390 4365 if (iocp->ioc_count != size)
4391 4366 return (IOC_INVAL);
4392 4367
4393 4368 value = 0;
4394 4369 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
4395 4370
4396 4371 lbpp[value++] = lb_normal;
4397 4372 lbpp[value++] = lb_mac;
4398 4373 lbpp[value++] = lb_external;
4399 4374 break;
4400 4375
4401 4376 case LB_GET_MODE:
4402 4377 size = sizeof (uint32_t);
4403 4378 if (iocp->ioc_count != size)
4404 4379 return (IOC_INVAL);
4405 4380
4406 4381 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
4407 4382 *lbmp = ixgbe->loopback_mode;
4408 4383 break;
4409 4384
4410 4385 case LB_SET_MODE:
4411 4386 size = 0;
4412 4387 if (iocp->ioc_count != sizeof (uint32_t))
4413 4388 return (IOC_INVAL);
4414 4389
4415 4390 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
4416 4391 if (!ixgbe_set_loopback_mode(ixgbe, *lbmp))
4417 4392 return (IOC_INVAL);
4418 4393 break;
4419 4394 }
4420 4395
4421 4396 iocp->ioc_count = size;
4422 4397 iocp->ioc_error = 0;
4423 4398
4424 4399 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4425 4400 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4426 4401 return (IOC_INVAL);
4427 4402 }
4428 4403
4429 4404 return (IOC_REPLY);
4430 4405 }
4431 4406
4432 4407 /*
4433 4408 * ixgbe_set_loopback_mode - Setup loopback based on the loopback mode.
4434 4409 */
4435 4410 static boolean_t
4436 4411 ixgbe_set_loopback_mode(ixgbe_t *ixgbe, uint32_t mode)
4437 4412 {
4438 4413 if (mode == ixgbe->loopback_mode)
4439 4414 return (B_TRUE);
4440 4415
4441 4416 ixgbe->loopback_mode = mode;
4442 4417
4443 4418 if (mode == IXGBE_LB_NONE) {
4444 4419 /*
4445 4420 * Reset the chip
4446 4421 */
4447 4422 (void) ixgbe_reset(ixgbe);
4448 4423 return (B_TRUE);
4449 4424 }
4450 4425
4451 4426 mutex_enter(&ixgbe->gen_lock);
4452 4427
4453 4428 switch (mode) {
4454 4429 default:
4455 4430 mutex_exit(&ixgbe->gen_lock);
4456 4431 return (B_FALSE);
4457 4432
4458 4433 case IXGBE_LB_EXTERNAL:
4459 4434 break;
4460 4435
4461 4436 case IXGBE_LB_INTERNAL_MAC:
4462 4437 ixgbe_set_internal_mac_loopback(ixgbe);
4463 4438 break;
4464 4439 }
4465 4440
4466 4441 mutex_exit(&ixgbe->gen_lock);
4467 4442
4468 4443 return (B_TRUE);
4469 4444 }
4470 4445
4471 4446 /*
4472 4447 * ixgbe_set_internal_mac_loopback - Set the internal MAC loopback mode.
4473 4448 */
4474 4449 static void
4475 4450 ixgbe_set_internal_mac_loopback(ixgbe_t *ixgbe)
4476 4451 {
4477 4452 struct ixgbe_hw *hw;
4478 4453 uint32_t reg;
4479 4454 uint8_t atlas;
4480 4455
4481 4456 hw = &ixgbe->hw;
4482 4457
4483 4458 /*
4484 4459 * Setup MAC loopback
4485 4460 */
4486 4461 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_HLREG0);
4487 4462 reg |= IXGBE_HLREG0_LPBK;
4488 4463 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_HLREG0, reg);
4489 4464
4490 4465 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
4491 4466 reg &= ~IXGBE_AUTOC_LMS_MASK;
4492 4467 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
4493 4468
4494 4469 /*
4495 4470 * Disable Atlas Tx lanes to keep packets in loopback and not on wire
4496 4471 */
4497 4472 switch (hw->mac.type) {
4498 4473 case ixgbe_mac_82598EB:
4499 4474 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
4500 4475 &atlas);
4501 4476 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
4502 4477 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
4503 4478 atlas);
4504 4479
4505 4480 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
4506 4481 &atlas);
4507 4482 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
4508 4483 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
4509 4484 atlas);
4510 4485
4511 4486 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
4512 4487 &atlas);
4513 4488 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
4514 4489 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
4515 4490 atlas);
4516 4491
4517 4492 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
4518 4493 &atlas);
4519 4494 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
4520 4495 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
4521 4496 atlas);
4522 4497 break;
4523 4498
4524 4499 case ixgbe_mac_82599EB:
4525 4500 case ixgbe_mac_X540:
4526 4501 case ixgbe_mac_X550:
4527 4502 case ixgbe_mac_X550EM_x:
4528 4503 case ixgbe_mac_X550EM_a:
4529 4504 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
4530 4505 reg |= (IXGBE_AUTOC_FLU |
4531 4506 IXGBE_AUTOC_10G_KX4);
4532 4507 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
4533 4508
4534 4509 (void) ixgbe_setup_link(&ixgbe->hw, IXGBE_LINK_SPEED_10GB_FULL,
4535 4510 B_FALSE);
4536 4511 break;
4537 4512
4538 4513 default:
4539 4514 break;
4540 4515 }
4541 4516 }
4542 4517
4543 4518 #pragma inline(ixgbe_intr_rx_work)
4544 4519 /*
4545 4520 * ixgbe_intr_rx_work - RX processing of ISR.
4546 4521 */
4547 4522 static void
4548 4523 ixgbe_intr_rx_work(ixgbe_rx_ring_t *rx_ring)
4549 4524 {
4550 4525 mblk_t *mp;
4551 4526
4552 4527 mutex_enter(&rx_ring->rx_lock);
4553 4528
4554 4529 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL);
4555 4530 mutex_exit(&rx_ring->rx_lock);
4556 4531
4557 4532 if (mp != NULL)
4558 4533 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
4559 4534 rx_ring->ring_gen_num);
4560 4535 }
4561 4536
4562 4537 #pragma inline(ixgbe_intr_tx_work)
4563 4538 /*
4564 4539 * ixgbe_intr_tx_work - TX processing of ISR.
4565 4540 */
4566 4541 static void
4567 4542 ixgbe_intr_tx_work(ixgbe_tx_ring_t *tx_ring)
4568 4543 {
4569 4544 ixgbe_t *ixgbe = tx_ring->ixgbe;
4570 4545
4571 4546 /*
4572 4547 * Recycle the tx descriptors
4573 4548 */
4574 4549 tx_ring->tx_recycle(tx_ring);
4575 4550
4576 4551 /*
4577 4552 * Schedule the re-transmit
4578 4553 */
4579 4554 if (tx_ring->reschedule &&
4580 4555 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh)) {
4581 4556 tx_ring->reschedule = B_FALSE;
4582 4557 mac_tx_ring_update(tx_ring->ixgbe->mac_hdl,
4583 4558 tx_ring->ring_handle);
4584 4559 tx_ring->stat_reschedule++;
4585 4560 }
4586 4561 }
4587 4562
4588 4563 #pragma inline(ixgbe_intr_other_work)
4589 4564 /*
4590 4565 * ixgbe_intr_other_work - Process interrupt types other than tx/rx
4591 4566 */
4592 4567 static void
4593 4568 ixgbe_intr_other_work(ixgbe_t *ixgbe, uint32_t eicr)
4594 4569 {
4595 4570 struct ixgbe_hw *hw = &ixgbe->hw;
4596 4571
4597 4572 ASSERT(mutex_owned(&ixgbe->gen_lock));
4598 4573
4599 4574 /*
4600 4575 * handle link status change
4601 4576 */
4602 4577 if (eicr & IXGBE_EICR_LSC) {
4603 4578 ixgbe_driver_link_check(ixgbe);
4604 4579 ixgbe_get_hw_state(ixgbe);
4605 4580 }
4606 4581
4607 4582 /*
4608 4583 * check for fan failure on adapters with fans
4609 4584 */
4610 4585 if ((ixgbe->capab->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
4611 4586 (eicr & IXGBE_EICR_GPI_SDP1)) {
4612 4587 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
4613 4588
4614 4589 /*
4615 4590 * Disable the adapter interrupts
4616 4591 */
4617 4592 ixgbe_disable_adapter_interrupts(ixgbe);
4618 4593
4619 4594 /*
4620 4595 * Disable Rx/Tx units
4621 4596 */
4622 4597 (void) ixgbe_stop_adapter(&ixgbe->hw);
4623 4598
4624 4599 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
4625 4600 ixgbe_error(ixgbe,
4626 4601 "Problem: Network adapter has been stopped "
4627 4602 "because the fan has stopped.\n");
4628 4603 ixgbe_error(ixgbe,
4629 4604 "Action: Replace the adapter.\n");
4630 4605
4631 4606 /* re-enable the interrupt, which was automasked */
4632 4607 ixgbe->eims |= IXGBE_EICR_GPI_SDP1;
4633 4608 }
4634 4609
4635 4610 /*
4636 4611 * Do SFP check for adapters with hot-plug capability
4637 4612 */
4638 4613 if ((ixgbe->capab->flags & IXGBE_FLAG_SFP_PLUG_CAPABLE) &&
4639 4614 ((eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw)) ||
4640 4615 (eicr & IXGBE_EICR_GPI_SDP2_BY_MAC(hw)))) {
4641 4616 ixgbe->eicr = eicr;
4642 4617 if ((ddi_taskq_dispatch(ixgbe->sfp_taskq,
4643 4618 ixgbe_sfp_check, (void *)ixgbe,
4644 4619 DDI_NOSLEEP)) != DDI_SUCCESS) {
4645 4620 ixgbe_log(ixgbe, "No memory available to dispatch "
4646 4621 "taskq for SFP check");
4647 4622 }
4648 4623 }
4649 4624
4650 4625 /*
4651 4626 * Do over-temperature check for adapters with temp sensor
4652 4627 */
4653 4628 if ((ixgbe->capab->flags & IXGBE_FLAG_TEMP_SENSOR_CAPABLE) &&
4654 4629 ((eicr & IXGBE_EICR_GPI_SDP0_BY_MAC(hw)) ||
4655 4630 (eicr & IXGBE_EICR_LSC))) {
4656 4631 ixgbe->eicr = eicr;
4657 4632 if ((ddi_taskq_dispatch(ixgbe->overtemp_taskq,
4658 4633 ixgbe_overtemp_check, (void *)ixgbe,
4659 4634 DDI_NOSLEEP)) != DDI_SUCCESS) {
4660 4635 ixgbe_log(ixgbe, "No memory available to dispatch "
4661 4636 "taskq for overtemp check");
4662 4637 }
4663 4638 }
4664 4639
4665 4640 /*
4666 4641 * Process an external PHY interrupt
4667 4642 */
4668 4643 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
4669 4644 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
4670 4645 ixgbe->eicr = eicr;
4671 4646 if ((ddi_taskq_dispatch(ixgbe->phy_taskq,
4672 4647 ixgbe_phy_check, (void *)ixgbe,
4673 4648 DDI_NOSLEEP)) != DDI_SUCCESS) {
4674 4649 ixgbe_log(ixgbe, "No memory available to dispatch "
4675 4650 "taskq for PHY check");
4676 4651 }
4677 4652 }
4678 4653 }
4679 4654
4680 4655 /*
4681 4656 * ixgbe_intr_legacy - Interrupt handler for legacy interrupts.
4682 4657 */
4683 4658 static uint_t
4684 4659 ixgbe_intr_legacy(void *arg1, void *arg2)
4685 4660 {
4686 4661 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4687 4662 struct ixgbe_hw *hw = &ixgbe->hw;
4688 4663 ixgbe_tx_ring_t *tx_ring;
4689 4664 ixgbe_rx_ring_t *rx_ring;
4690 4665 uint32_t eicr;
4691 4666 mblk_t *mp;
4692 4667 boolean_t tx_reschedule;
4693 4668 uint_t result;
4694 4669
4695 4670 _NOTE(ARGUNUSED(arg2));
4696 4671
4697 4672 mutex_enter(&ixgbe->gen_lock);
4698 4673 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
4699 4674 mutex_exit(&ixgbe->gen_lock);
4700 4675 return (DDI_INTR_UNCLAIMED);
4701 4676 }
4702 4677
4703 4678 mp = NULL;
4704 4679 tx_reschedule = B_FALSE;
4705 4680
4706 4681 /*
4707 4682 * Any bit set in eicr: claim this interrupt
4708 4683 */
4709 4684 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4710 4685
4711 4686 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4712 4687 mutex_exit(&ixgbe->gen_lock);
4713 4688 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4714 4689 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4715 4690 return (DDI_INTR_CLAIMED);
4716 4691 }
4717 4692
4718 4693 if (eicr) {
4719 4694 /*
4720 4695 * For legacy interrupt, we have only one interrupt,
4721 4696 * so we have only one rx ring and one tx ring enabled.
4722 4697 */
4723 4698 ASSERT(ixgbe->num_rx_rings == 1);
4724 4699 ASSERT(ixgbe->num_tx_rings == 1);
4725 4700
4726 4701 /*
4727 4702 * For legacy interrupt, rx rings[0] will use RTxQ[0].
4728 4703 */
4729 4704 if (eicr & 0x1) {
4730 4705 ixgbe->eimc |= IXGBE_EICR_RTX_QUEUE;
4731 4706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4732 4707 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4733 4708 /*
4734 4709 * Clean the rx descriptors
4735 4710 */
4736 4711 rx_ring = &ixgbe->rx_rings[0];
4737 4712 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL);
4738 4713 }
4739 4714
4740 4715 /*
4741 4716 * For legacy interrupt, tx rings[0] will use RTxQ[1].
4742 4717 */
4743 4718 if (eicr & 0x2) {
4744 4719 /*
4745 4720 * Recycle the tx descriptors
4746 4721 */
4747 4722 tx_ring = &ixgbe->tx_rings[0];
4748 4723 tx_ring->tx_recycle(tx_ring);
4749 4724
4750 4725 /*
4751 4726 * Schedule the re-transmit
4752 4727 */
4753 4728 tx_reschedule = (tx_ring->reschedule &&
4754 4729 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh));
4755 4730 }
4756 4731
4757 4732 /* any interrupt type other than tx/rx */
4758 4733 if (eicr & ixgbe->capab->other_intr) {
4759 4734 switch (hw->mac.type) {
4760 4735 case ixgbe_mac_82598EB:
4761 4736 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4762 4737 break;
4763 4738
4764 4739 case ixgbe_mac_82599EB:
4765 4740 case ixgbe_mac_X540:
4766 4741 case ixgbe_mac_X550:
4767 4742 case ixgbe_mac_X550EM_x:
4768 4743 case ixgbe_mac_X550EM_a:
4769 4744 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4770 4745 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4771 4746 break;
4772 4747
4773 4748 default:
4774 4749 break;
4775 4750 }
4776 4751 ixgbe_intr_other_work(ixgbe, eicr);
4777 4752 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4778 4753 }
4779 4754
4780 4755 mutex_exit(&ixgbe->gen_lock);
4781 4756
4782 4757 result = DDI_INTR_CLAIMED;
4783 4758 } else {
4784 4759 mutex_exit(&ixgbe->gen_lock);
4785 4760
4786 4761 /*
4787 4762 * No interrupt cause bits set: don't claim this interrupt.
4788 4763 */
4789 4764 result = DDI_INTR_UNCLAIMED;
4790 4765 }
4791 4766
4792 4767 /* re-enable the interrupts which were automasked */
4793 4768 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4794 4769
4795 4770 /*
4796 4771 * Do the following work outside of the gen_lock
4797 4772 */
4798 4773 if (mp != NULL) {
4799 4774 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
4800 4775 rx_ring->ring_gen_num);
4801 4776 }
4802 4777
4803 4778 if (tx_reschedule) {
4804 4779 tx_ring->reschedule = B_FALSE;
4805 4780 mac_tx_ring_update(ixgbe->mac_hdl, tx_ring->ring_handle);
4806 4781 tx_ring->stat_reschedule++;
4807 4782 }
4808 4783
4809 4784 return (result);
4810 4785 }
4811 4786
4812 4787 /*
4813 4788 * ixgbe_intr_msi - Interrupt handler for MSI.
4814 4789 */
4815 4790 static uint_t
4816 4791 ixgbe_intr_msi(void *arg1, void *arg2)
4817 4792 {
4818 4793 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4819 4794 struct ixgbe_hw *hw = &ixgbe->hw;
4820 4795 uint32_t eicr;
4821 4796
4822 4797 _NOTE(ARGUNUSED(arg2));
4823 4798
4824 4799 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4825 4800
4826 4801 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4827 4802 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4828 4803 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4829 4804 return (DDI_INTR_CLAIMED);
4830 4805 }
4831 4806
4832 4807 /*
4833 4808 * For MSI interrupt, we have only one vector,
4834 4809 * so we have only one rx ring and one tx ring enabled.
4835 4810 */
4836 4811 ASSERT(ixgbe->num_rx_rings == 1);
4837 4812 ASSERT(ixgbe->num_tx_rings == 1);
4838 4813
4839 4814 /*
4840 4815 * For MSI interrupt, rx rings[0] will use RTxQ[0].
4841 4816 */
4842 4817 if (eicr & 0x1) {
4843 4818 ixgbe_intr_rx_work(&ixgbe->rx_rings[0]);
4844 4819 }
4845 4820
4846 4821 /*
4847 4822 * For MSI interrupt, tx rings[0] will use RTxQ[1].
4848 4823 */
4849 4824 if (eicr & 0x2) {
4850 4825 ixgbe_intr_tx_work(&ixgbe->tx_rings[0]);
4851 4826 }
4852 4827
4853 4828 /* any interrupt type other than tx/rx */
4854 4829 if (eicr & ixgbe->capab->other_intr) {
4855 4830 mutex_enter(&ixgbe->gen_lock);
4856 4831 switch (hw->mac.type) {
4857 4832 case ixgbe_mac_82598EB:
4858 4833 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4859 4834 break;
4860 4835
4861 4836 case ixgbe_mac_82599EB:
4862 4837 case ixgbe_mac_X540:
4863 4838 case ixgbe_mac_X550:
4864 4839 case ixgbe_mac_X550EM_x:
4865 4840 case ixgbe_mac_X550EM_a:
4866 4841 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4867 4842 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4868 4843 break;
4869 4844
4870 4845 default:
4871 4846 break;
4872 4847 }
4873 4848 ixgbe_intr_other_work(ixgbe, eicr);
4874 4849 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4875 4850 mutex_exit(&ixgbe->gen_lock);
4876 4851 }
4877 4852
4878 4853 /* re-enable the interrupts which were automasked */
4879 4854 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4880 4855
4881 4856 return (DDI_INTR_CLAIMED);
4882 4857 }
4883 4858
4884 4859 /*
4885 4860 * ixgbe_intr_msix - Interrupt handler for MSI-X.
4886 4861 */
4887 4862 static uint_t
4888 4863 ixgbe_intr_msix(void *arg1, void *arg2)
4889 4864 {
4890 4865 ixgbe_intr_vector_t *vect = (ixgbe_intr_vector_t *)arg1;
4891 4866 ixgbe_t *ixgbe = vect->ixgbe;
4892 4867 struct ixgbe_hw *hw = &ixgbe->hw;
4893 4868 uint32_t eicr;
4894 4869 int r_idx = 0;
4895 4870
4896 4871 _NOTE(ARGUNUSED(arg2));
4897 4872
4898 4873 /*
4899 4874 * Clean each rx ring that has its bit set in the map
4900 4875 */
4901 4876 r_idx = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1));
4902 4877 while (r_idx >= 0) {
4903 4878 ixgbe_intr_rx_work(&ixgbe->rx_rings[r_idx]);
4904 4879 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1),
4905 4880 (ixgbe->num_rx_rings - 1));
4906 4881 }
4907 4882
4908 4883 /*
4909 4884 * Clean each tx ring that has its bit set in the map
4910 4885 */
4911 4886 r_idx = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1));
4912 4887 while (r_idx >= 0) {
4913 4888 ixgbe_intr_tx_work(&ixgbe->tx_rings[r_idx]);
4914 4889 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1),
4915 4890 (ixgbe->num_tx_rings - 1));
4916 4891 }
4917 4892
4918 4893
4919 4894 /*
4920 4895 * Clean other interrupt (link change) that has its bit set in the map
4921 4896 */
4922 4897 if (BT_TEST(vect->other_map, 0) == 1) {
4923 4898 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4924 4899
4925 4900 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) !=
4926 4901 DDI_FM_OK) {
4927 4902 ddi_fm_service_impact(ixgbe->dip,
4928 4903 DDI_SERVICE_DEGRADED);
4929 4904 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4930 4905 return (DDI_INTR_CLAIMED);
4931 4906 }
4932 4907
4933 4908 /*
4934 4909 * Check "other" cause bits: any interrupt type other than tx/rx
4935 4910 */
4936 4911 if (eicr & ixgbe->capab->other_intr) {
4937 4912 mutex_enter(&ixgbe->gen_lock);
4938 4913 switch (hw->mac.type) {
4939 4914 case ixgbe_mac_82598EB:
4940 4915 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4941 4916 ixgbe_intr_other_work(ixgbe, eicr);
4942 4917 break;
4943 4918
4944 4919 case ixgbe_mac_82599EB:
4945 4920 case ixgbe_mac_X540:
4946 4921 case ixgbe_mac_X550:
4947 4922 case ixgbe_mac_X550EM_x:
4948 4923 case ixgbe_mac_X550EM_a:
4949 4924 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4950 4925 ixgbe_intr_other_work(ixgbe, eicr);
4951 4926 break;
4952 4927
4953 4928 default:
4954 4929 break;
4955 4930 }
4956 4931 mutex_exit(&ixgbe->gen_lock);
4957 4932 }
4958 4933
4959 4934 /* re-enable the interrupts which were automasked */
4960 4935 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4961 4936 }
4962 4937
4963 4938 return (DDI_INTR_CLAIMED);
4964 4939 }
4965 4940
4966 4941 /*
4967 4942 * ixgbe_alloc_intrs - Allocate interrupts for the driver.
4968 4943 *
4969 4944 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4970 4945 * if not successful, try Legacy.
4971 4946 * ixgbe->intr_force can be used to force sequence to start with
4972 4947 * any of the 3 types.
4973 4948 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4974 4949 */
4975 4950 static int
4976 4951 ixgbe_alloc_intrs(ixgbe_t *ixgbe)
4977 4952 {
4978 4953 dev_info_t *devinfo;
4979 4954 int intr_types;
4980 4955 int rc;
4981 4956
4982 4957 devinfo = ixgbe->dip;
4983 4958
4984 4959 /*
4985 4960 * Get supported interrupt types
4986 4961 */
4987 4962 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4988 4963
4989 4964 if (rc != DDI_SUCCESS) {
4990 4965 ixgbe_log(ixgbe,
4991 4966 "Get supported interrupt types failed: %d", rc);
4992 4967 return (IXGBE_FAILURE);
4993 4968 }
4994 4969 IXGBE_DEBUGLOG_1(ixgbe, "Supported interrupt types: %x", intr_types);
4995 4970
4996 4971 ixgbe->intr_type = 0;
4997 4972
4998 4973 /*
4999 4974 * Install MSI-X interrupts
5000 4975 */
5001 4976 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
5002 4977 (ixgbe->intr_force <= IXGBE_INTR_MSIX)) {
5003 4978 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSIX);
5004 4979 if (rc == IXGBE_SUCCESS)
5005 4980 return (IXGBE_SUCCESS);
5006 4981
5007 4982 ixgbe_log(ixgbe,
5008 4983 "Allocate MSI-X failed, trying MSI interrupts...");
5009 4984 }
5010 4985
5011 4986 /*
5012 4987 * MSI-X not used, force rings and groups to 1
5013 4988 */
5014 4989 ixgbe->num_rx_rings = 1;
5015 4990 ixgbe->num_rx_groups = 1;
5016 4991 ixgbe->num_tx_rings = 1;
5017 4992 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
5018 4993 ixgbe_log(ixgbe,
5019 4994 "MSI-X not used, force rings and groups number to 1");
5020 4995
5021 4996 /*
5022 4997 * Install MSI interrupts
5023 4998 */
5024 4999 if ((intr_types & DDI_INTR_TYPE_MSI) &&
5025 5000 (ixgbe->intr_force <= IXGBE_INTR_MSI)) {
5026 5001 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSI);
5027 5002 if (rc == IXGBE_SUCCESS)
5028 5003 return (IXGBE_SUCCESS);
5029 5004
5030 5005 ixgbe_log(ixgbe,
5031 5006 "Allocate MSI failed, trying Legacy interrupts...");
5032 5007 }
5033 5008
5034 5009 /*
5035 5010 * Install legacy interrupts
5036 5011 */
5037 5012 if (intr_types & DDI_INTR_TYPE_FIXED) {
5038 5013 /*
5039 5014 * Disallow legacy interrupts for X550. X550 has a silicon
5040 5015 * bug which prevents Shared Legacy interrupts from working.
5041 5016 * For details, please reference:
5042 5017 *
5043 5018 * Intel Ethernet Controller X550 Specification Update rev. 2.1
5044 5019 * May 2016, erratum 22: PCIe Interrupt Status Bit
5045 5020 */
5046 5021 if (ixgbe->hw.mac.type == ixgbe_mac_X550 ||
5047 5022 ixgbe->hw.mac.type == ixgbe_mac_X550EM_x ||
5048 5023 ixgbe->hw.mac.type == ixgbe_mac_X550EM_a ||
5049 5024 ixgbe->hw.mac.type == ixgbe_mac_X550_vf ||
5050 5025 ixgbe->hw.mac.type == ixgbe_mac_X550EM_x_vf ||
5051 5026 ixgbe->hw.mac.type == ixgbe_mac_X550EM_a_vf) {
5052 5027 ixgbe_log(ixgbe,
5053 5028 "Legacy interrupts are not supported on this "
5054 5029 "adapter. Please use MSI or MSI-X instead.");
5055 5030 return (IXGBE_FAILURE);
5056 5031 }
5057 5032 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_FIXED);
5058 5033 if (rc == IXGBE_SUCCESS)
5059 5034 return (IXGBE_SUCCESS);
5060 5035
5061 5036 ixgbe_log(ixgbe,
5062 5037 "Allocate Legacy interrupts failed");
5063 5038 }
5064 5039
5065 5040 /*
5066 5041 * If none of the 3 types succeeded, return failure
5067 5042 */
5068 5043 return (IXGBE_FAILURE);
5069 5044 }
5070 5045
5071 5046 /*
5072 5047 * ixgbe_alloc_intr_handles - Allocate interrupt handles.
5073 5048 *
5074 5049 * For legacy and MSI, only 1 handle is needed. For MSI-X,
5075 5050 * if fewer than 2 handles are available, return failure.
5076 5051 * Upon success, this maps the vectors to rx and tx rings for
5077 5052 * interrupts.
5078 5053 */
5079 5054 static int
5080 5055 ixgbe_alloc_intr_handles(ixgbe_t *ixgbe, int intr_type)
5081 5056 {
5082 5057 dev_info_t *devinfo;
5083 5058 int request, count, actual;
5084 5059 int minimum;
5085 5060 int rc;
5086 5061 uint32_t ring_per_group;
5087 5062
5088 5063 devinfo = ixgbe->dip;
5089 5064
5090 5065 switch (intr_type) {
5091 5066 case DDI_INTR_TYPE_FIXED:
5092 5067 request = 1; /* Request 1 legacy interrupt handle */
5093 5068 minimum = 1;
5094 5069 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: legacy");
5095 5070 break;
5096 5071
5097 5072 case DDI_INTR_TYPE_MSI:
5098 5073 request = 1; /* Request 1 MSI interrupt handle */
5099 5074 minimum = 1;
5100 5075 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI");
5101 5076 break;
5102 5077
5103 5078 case DDI_INTR_TYPE_MSIX:
5104 5079 /*
5105 5080 * Best number of vectors for the adapter is
5106 5081 * (# rx rings + # tx rings), however we will
5107 5082 * limit the request number.
5108 5083 */
5109 5084 request = min(16, ixgbe->num_rx_rings + ixgbe->num_tx_rings);
5110 5085 if (request > ixgbe->capab->max_ring_vect)
5111 5086 request = ixgbe->capab->max_ring_vect;
5112 5087 minimum = 1;
5113 5088 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI-X");
5114 5089 break;
5115 5090
5116 5091 default:
5117 5092 ixgbe_log(ixgbe,
5118 5093 "invalid call to ixgbe_alloc_intr_handles(): %d\n",
5119 5094 intr_type);
5120 5095 return (IXGBE_FAILURE);
5121 5096 }
5122 5097 IXGBE_DEBUGLOG_2(ixgbe, "interrupt handles requested: %d minimum: %d",
5123 5098 request, minimum);
5124 5099
5125 5100 /*
5126 5101 * Get number of supported interrupts
5127 5102 */
5128 5103 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
5129 5104 if ((rc != DDI_SUCCESS) || (count < minimum)) {
5130 5105 ixgbe_log(ixgbe,
5131 5106 "Get interrupt number failed. Return: %d, count: %d",
5132 5107 rc, count);
5133 5108 return (IXGBE_FAILURE);
5134 5109 }
5135 5110 IXGBE_DEBUGLOG_1(ixgbe, "interrupts supported: %d", count);
5136 5111
5137 5112 actual = 0;
5138 5113 ixgbe->intr_cnt = 0;
5139 5114 ixgbe->intr_cnt_max = 0;
5140 5115 ixgbe->intr_cnt_min = 0;
5141 5116
5142 5117 /*
5143 5118 * Allocate an array of interrupt handles
5144 5119 */
5145 5120 ixgbe->intr_size = request * sizeof (ddi_intr_handle_t);
5146 5121 ixgbe->htable = kmem_alloc(ixgbe->intr_size, KM_SLEEP);
5147 5122
5148 5123 rc = ddi_intr_alloc(devinfo, ixgbe->htable, intr_type, 0,
5149 5124 request, &actual, DDI_INTR_ALLOC_NORMAL);
5150 5125 if (rc != DDI_SUCCESS) {
5151 5126 ixgbe_log(ixgbe, "Allocate interrupts failed. "
5152 5127 "return: %d, request: %d, actual: %d",
5153 5128 rc, request, actual);
5154 5129 goto alloc_handle_fail;
5155 5130 }
5156 5131 IXGBE_DEBUGLOG_1(ixgbe, "interrupts actually allocated: %d", actual);
5157 5132
5158 5133 /*
5159 5134 * upper/lower limit of interrupts
5160 5135 */
5161 5136 ixgbe->intr_cnt = actual;
5162 5137 ixgbe->intr_cnt_max = request;
5163 5138 ixgbe->intr_cnt_min = minimum;
5164 5139
5165 5140 /*
5166 5141 * rss number per group should not exceed the rx interrupt number,
5167 5142 * else need to adjust rx ring number.
5168 5143 */
5169 5144 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
5170 5145 ASSERT((ixgbe->num_rx_rings % ixgbe->num_rx_groups) == 0);
5171 5146 if (actual < ring_per_group) {
5172 5147 ixgbe->num_rx_rings = ixgbe->num_rx_groups * actual;
5173 5148 ixgbe_setup_vmdq_rss_conf(ixgbe);
5174 5149 }
5175 5150
5176 5151 /*
5177 5152 * Now we know the actual number of vectors. Here we map the vector
5178 5153 * to other, rx rings and tx ring.
5179 5154 */
5180 5155 if (actual < minimum) {
5181 5156 ixgbe_log(ixgbe, "Insufficient interrupt handles available: %d",
5182 5157 actual);
5183 5158 goto alloc_handle_fail;
5184 5159 }
5185 5160
5186 5161 /*
5187 5162 * Get priority for first vector, assume remaining are all the same
5188 5163 */
5189 5164 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
5190 5165 if (rc != DDI_SUCCESS) {
5191 5166 ixgbe_log(ixgbe,
5192 5167 "Get interrupt priority failed: %d", rc);
5193 5168 goto alloc_handle_fail;
5194 5169 }
5195 5170
5196 5171 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
5197 5172 if (rc != DDI_SUCCESS) {
5198 5173 ixgbe_log(ixgbe,
5199 5174 "Get interrupt cap failed: %d", rc);
5200 5175 goto alloc_handle_fail;
5201 5176 }
5202 5177
5203 5178 ixgbe->intr_type = intr_type;
5204 5179
5205 5180 return (IXGBE_SUCCESS);
5206 5181
5207 5182 alloc_handle_fail:
5208 5183 ixgbe_rem_intrs(ixgbe);
5209 5184
5210 5185 return (IXGBE_FAILURE);
5211 5186 }
5212 5187
5213 5188 /*
5214 5189 * ixgbe_add_intr_handlers - Add interrupt handlers based on the interrupt type.
5215 5190 *
5216 5191 * Before adding the interrupt handlers, the interrupt vectors have
5217 5192 * been allocated, and the rx/tx rings have also been allocated.
5218 5193 */
5219 5194 static int
5220 5195 ixgbe_add_intr_handlers(ixgbe_t *ixgbe)
5221 5196 {
5222 5197 int vector = 0;
5223 5198 int rc;
5224 5199
5225 5200 switch (ixgbe->intr_type) {
5226 5201 case DDI_INTR_TYPE_MSIX:
5227 5202 /*
5228 5203 * Add interrupt handler for all vectors
5229 5204 */
5230 5205 for (vector = 0; vector < ixgbe->intr_cnt; vector++) {
5231 5206 /*
5232 5207 * install pointer to vect_map[vector]
5233 5208 */
5234 5209 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5235 5210 (ddi_intr_handler_t *)ixgbe_intr_msix,
5236 5211 (void *)&ixgbe->vect_map[vector], NULL);
5237 5212
5238 5213 if (rc != DDI_SUCCESS) {
5239 5214 ixgbe_log(ixgbe,
5240 5215 "Add interrupt handler failed. "
5241 5216 "return: %d, vector: %d", rc, vector);
5242 5217 for (vector--; vector >= 0; vector--) {
5243 5218 (void) ddi_intr_remove_handler(
5244 5219 ixgbe->htable[vector]);
5245 5220 }
5246 5221 return (IXGBE_FAILURE);
5247 5222 }
5248 5223 }
5249 5224
5250 5225 break;
5251 5226
5252 5227 case DDI_INTR_TYPE_MSI:
5253 5228 /*
5254 5229 * Add interrupt handlers for the only vector
5255 5230 */
5256 5231 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5257 5232 (ddi_intr_handler_t *)ixgbe_intr_msi,
5258 5233 (void *)ixgbe, NULL);
5259 5234
5260 5235 if (rc != DDI_SUCCESS) {
5261 5236 ixgbe_log(ixgbe,
5262 5237 "Add MSI interrupt handler failed: %d", rc);
5263 5238 return (IXGBE_FAILURE);
5264 5239 }
5265 5240
5266 5241 break;
5267 5242
5268 5243 case DDI_INTR_TYPE_FIXED:
5269 5244 /*
5270 5245 * Add interrupt handlers for the only vector
5271 5246 */
5272 5247 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5273 5248 (ddi_intr_handler_t *)ixgbe_intr_legacy,
5274 5249 (void *)ixgbe, NULL);
5275 5250
5276 5251 if (rc != DDI_SUCCESS) {
5277 5252 ixgbe_log(ixgbe,
5278 5253 "Add legacy interrupt handler failed: %d", rc);
5279 5254 return (IXGBE_FAILURE);
5280 5255 }
5281 5256
5282 5257 break;
5283 5258
5284 5259 default:
5285 5260 return (IXGBE_FAILURE);
5286 5261 }
5287 5262
5288 5263 return (IXGBE_SUCCESS);
5289 5264 }
5290 5265
5291 5266 #pragma inline(ixgbe_map_rxring_to_vector)
5292 5267 /*
5293 5268 * ixgbe_map_rxring_to_vector - Map given rx ring to given interrupt vector.
5294 5269 */
5295 5270 static void
5296 5271 ixgbe_map_rxring_to_vector(ixgbe_t *ixgbe, int r_idx, int v_idx)
5297 5272 {
5298 5273 /*
5299 5274 * Set bit in map
5300 5275 */
5301 5276 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
5302 5277
5303 5278 /*
5304 5279 * Count bits set
5305 5280 */
5306 5281 ixgbe->vect_map[v_idx].rxr_cnt++;
5307 5282
5308 5283 /*
5309 5284 * Remember bit position
5310 5285 */
5311 5286 ixgbe->rx_rings[r_idx].intr_vector = v_idx;
5312 5287 ixgbe->rx_rings[r_idx].vect_bit = 1 << v_idx;
5313 5288 }
5314 5289
5315 5290 #pragma inline(ixgbe_map_txring_to_vector)
5316 5291 /*
5317 5292 * ixgbe_map_txring_to_vector - Map given tx ring to given interrupt vector.
5318 5293 */
5319 5294 static void
5320 5295 ixgbe_map_txring_to_vector(ixgbe_t *ixgbe, int t_idx, int v_idx)
5321 5296 {
5322 5297 /*
5323 5298 * Set bit in map
5324 5299 */
5325 5300 BT_SET(ixgbe->vect_map[v_idx].tx_map, t_idx);
5326 5301
5327 5302 /*
5328 5303 * Count bits set
5329 5304 */
5330 5305 ixgbe->vect_map[v_idx].txr_cnt++;
5331 5306
5332 5307 /*
5333 5308 * Remember bit position
5334 5309 */
5335 5310 ixgbe->tx_rings[t_idx].intr_vector = v_idx;
5336 5311 ixgbe->tx_rings[t_idx].vect_bit = 1 << v_idx;
5337 5312 }
5338 5313
5339 5314 /*
5340 5315 * ixgbe_setup_ivar - Set the given entry in the given interrupt vector
5341 5316 * allocation register (IVAR).
5342 5317 * cause:
5343 5318 * -1 : other cause
5344 5319 * 0 : rx
5345 5320 * 1 : tx
5346 5321 */
5347 5322 static void
5348 5323 ixgbe_setup_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, uint8_t msix_vector,
5349 5324 int8_t cause)
5350 5325 {
5351 5326 struct ixgbe_hw *hw = &ixgbe->hw;
5352 5327 u32 ivar, index;
5353 5328
5354 5329 switch (hw->mac.type) {
5355 5330 case ixgbe_mac_82598EB:
5356 5331 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5357 5332 if (cause == -1) {
5358 5333 cause = 0;
5359 5334 }
5360 5335 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
5361 5336 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
5362 5337 ivar &= ~(0xFF << (8 * (intr_alloc_entry & 0x3)));
5363 5338 ivar |= (msix_vector << (8 * (intr_alloc_entry & 0x3)));
5364 5339 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
5365 5340 break;
5366 5341
5367 5342 case ixgbe_mac_82599EB:
5368 5343 case ixgbe_mac_X540:
5369 5344 case ixgbe_mac_X550:
5370 5345 case ixgbe_mac_X550EM_x:
5371 5346 case ixgbe_mac_X550EM_a:
5372 5347 if (cause == -1) {
5373 5348 /* other causes */
5374 5349 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5375 5350 index = (intr_alloc_entry & 1) * 8;
5376 5351 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5377 5352 ivar &= ~(0xFF << index);
5378 5353 ivar |= (msix_vector << index);
5379 5354 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
5380 5355 } else {
5381 5356 /* tx or rx causes */
5382 5357 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5383 5358 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
5384 5359 ivar = IXGBE_READ_REG(hw,
5385 5360 IXGBE_IVAR(intr_alloc_entry >> 1));
5386 5361 ivar &= ~(0xFF << index);
5387 5362 ivar |= (msix_vector << index);
5388 5363 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
5389 5364 ivar);
5390 5365 }
5391 5366 break;
5392 5367
5393 5368 default:
5394 5369 break;
5395 5370 }
5396 5371 }
5397 5372
5398 5373 /*
5399 5374 * ixgbe_enable_ivar - Enable the given entry by setting the VAL bit of
5400 5375 * given interrupt vector allocation register (IVAR).
5401 5376 * cause:
5402 5377 * -1 : other cause
5403 5378 * 0 : rx
5404 5379 * 1 : tx
5405 5380 */
5406 5381 static void
5407 5382 ixgbe_enable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
5408 5383 {
5409 5384 struct ixgbe_hw *hw = &ixgbe->hw;
5410 5385 u32 ivar, index;
5411 5386
5412 5387 switch (hw->mac.type) {
5413 5388 case ixgbe_mac_82598EB:
5414 5389 if (cause == -1) {
5415 5390 cause = 0;
5416 5391 }
5417 5392 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
5418 5393 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
5419 5394 ivar |= (IXGBE_IVAR_ALLOC_VAL << (8 *
5420 5395 (intr_alloc_entry & 0x3)));
5421 5396 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
5422 5397 break;
5423 5398
5424 5399 case ixgbe_mac_82599EB:
5425 5400 case ixgbe_mac_X540:
5426 5401 case ixgbe_mac_X550:
5427 5402 case ixgbe_mac_X550EM_x:
5428 5403 case ixgbe_mac_X550EM_a:
5429 5404 if (cause == -1) {
5430 5405 /* other causes */
5431 5406 index = (intr_alloc_entry & 1) * 8;
5432 5407 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5433 5408 ivar |= (IXGBE_IVAR_ALLOC_VAL << index);
5434 5409 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
5435 5410 } else {
5436 5411 /* tx or rx causes */
5437 5412 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
5438 5413 ivar = IXGBE_READ_REG(hw,
5439 5414 IXGBE_IVAR(intr_alloc_entry >> 1));
5440 5415 ivar |= (IXGBE_IVAR_ALLOC_VAL << index);
5441 5416 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
5442 5417 ivar);
5443 5418 }
5444 5419 break;
5445 5420
5446 5421 default:
5447 5422 break;
5448 5423 }
5449 5424 }
5450 5425
5451 5426 /*
5452 5427 * ixgbe_disable_ivar - Disble the given entry by clearing the VAL bit of
5453 5428 * given interrupt vector allocation register (IVAR).
5454 5429 * cause:
5455 5430 * -1 : other cause
5456 5431 * 0 : rx
5457 5432 * 1 : tx
5458 5433 */
5459 5434 static void
5460 5435 ixgbe_disable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
5461 5436 {
5462 5437 struct ixgbe_hw *hw = &ixgbe->hw;
5463 5438 u32 ivar, index;
5464 5439
5465 5440 switch (hw->mac.type) {
5466 5441 case ixgbe_mac_82598EB:
5467 5442 if (cause == -1) {
5468 5443 cause = 0;
5469 5444 }
5470 5445 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
5471 5446 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
5472 5447 ivar &= ~(IXGBE_IVAR_ALLOC_VAL<< (8 *
5473 5448 (intr_alloc_entry & 0x3)));
5474 5449 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
5475 5450 break;
5476 5451
5477 5452 case ixgbe_mac_82599EB:
5478 5453 case ixgbe_mac_X540:
5479 5454 case ixgbe_mac_X550:
5480 5455 case ixgbe_mac_X550EM_x:
5481 5456 case ixgbe_mac_X550EM_a:
5482 5457 if (cause == -1) {
5483 5458 /* other causes */
5484 5459 index = (intr_alloc_entry & 1) * 8;
5485 5460 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5486 5461 ivar &= ~(IXGBE_IVAR_ALLOC_VAL << index);
5487 5462 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
5488 5463 } else {
5489 5464 /* tx or rx causes */
5490 5465 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
5491 5466 ivar = IXGBE_READ_REG(hw,
5492 5467 IXGBE_IVAR(intr_alloc_entry >> 1));
5493 5468 ivar &= ~(IXGBE_IVAR_ALLOC_VAL << index);
5494 5469 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
5495 5470 ivar);
5496 5471 }
5497 5472 break;
5498 5473
5499 5474 default:
5500 5475 break;
5501 5476 }
5502 5477 }
5503 5478
5504 5479 /*
5505 5480 * Convert the rx ring index driver maintained to the rx ring index
5506 5481 * in h/w.
5507 5482 */
5508 5483 static uint32_t
5509 5484 ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index)
5510 5485 {
5511 5486
5512 5487 struct ixgbe_hw *hw = &ixgbe->hw;
5513 5488 uint32_t rx_ring_per_group, hw_rx_index;
5514 5489
5515 5490 if (ixgbe->classify_mode == IXGBE_CLASSIFY_RSS ||
5516 5491 ixgbe->classify_mode == IXGBE_CLASSIFY_NONE) {
5517 5492 return (sw_rx_index);
5518 5493 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ) {
5519 5494 switch (hw->mac.type) {
5520 5495 case ixgbe_mac_82598EB:
5521 5496 return (sw_rx_index);
5522 5497
5523 5498 case ixgbe_mac_82599EB:
5524 5499 case ixgbe_mac_X540:
5525 5500 case ixgbe_mac_X550:
5526 5501 case ixgbe_mac_X550EM_x:
5527 5502 case ixgbe_mac_X550EM_a:
5528 5503 return (sw_rx_index * 2);
5529 5504
5530 5505 default:
5531 5506 break;
5532 5507 }
5533 5508 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ_RSS) {
5534 5509 rx_ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
5535 5510
5536 5511 switch (hw->mac.type) {
5537 5512 case ixgbe_mac_82598EB:
5538 5513 hw_rx_index = (sw_rx_index / rx_ring_per_group) *
5539 5514 16 + (sw_rx_index % rx_ring_per_group);
5540 5515 return (hw_rx_index);
5541 5516
5542 5517 case ixgbe_mac_82599EB:
5543 5518 case ixgbe_mac_X540:
5544 5519 case ixgbe_mac_X550:
5545 5520 case ixgbe_mac_X550EM_x:
5546 5521 case ixgbe_mac_X550EM_a:
5547 5522 if (ixgbe->num_rx_groups > 32) {
5548 5523 hw_rx_index = (sw_rx_index /
5549 5524 rx_ring_per_group) * 2 +
5550 5525 (sw_rx_index % rx_ring_per_group);
5551 5526 } else {
5552 5527 hw_rx_index = (sw_rx_index /
5553 5528 rx_ring_per_group) * 4 +
5554 5529 (sw_rx_index % rx_ring_per_group);
5555 5530 }
5556 5531 return (hw_rx_index);
5557 5532
5558 5533 default:
5559 5534 break;
5560 5535 }
5561 5536 }
5562 5537
5563 5538 /*
5564 5539 * Should never reach. Just to make compiler happy.
5565 5540 */
5566 5541 return (sw_rx_index);
5567 5542 }
5568 5543
5569 5544 /*
5570 5545 * ixgbe_map_intrs_to_vectors - Map different interrupts to MSI-X vectors.
5571 5546 *
5572 5547 * For MSI-X, here will map rx interrupt, tx interrupt and other interrupt
5573 5548 * to vector[0 - (intr_cnt -1)].
5574 5549 */
5575 5550 static int
5576 5551 ixgbe_map_intrs_to_vectors(ixgbe_t *ixgbe)
5577 5552 {
5578 5553 int i, vector = 0;
5579 5554
5580 5555 /* initialize vector map */
5581 5556 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
5582 5557 for (i = 0; i < ixgbe->intr_cnt; i++) {
5583 5558 ixgbe->vect_map[i].ixgbe = ixgbe;
5584 5559 }
5585 5560
5586 5561 /*
5587 5562 * non-MSI-X case is very simple: rx rings[0] on RTxQ[0],
5588 5563 * tx rings[0] on RTxQ[1].
5589 5564 */
5590 5565 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
5591 5566 ixgbe_map_rxring_to_vector(ixgbe, 0, 0);
5592 5567 ixgbe_map_txring_to_vector(ixgbe, 0, 1);
5593 5568 return (IXGBE_SUCCESS);
5594 5569 }
5595 5570
5596 5571 /*
5597 5572 * Interrupts/vectors mapping for MSI-X
5598 5573 */
5599 5574
5600 5575 /*
5601 5576 * Map other interrupt to vector 0,
5602 5577 * Set bit in map and count the bits set.
5603 5578 */
5604 5579 BT_SET(ixgbe->vect_map[vector].other_map, 0);
5605 5580 ixgbe->vect_map[vector].other_cnt++;
5606 5581
5607 5582 /*
5608 5583 * Map rx ring interrupts to vectors
5609 5584 */
5610 5585 for (i = 0; i < ixgbe->num_rx_rings; i++) {
5611 5586 ixgbe_map_rxring_to_vector(ixgbe, i, vector);
5612 5587 vector = (vector +1) % ixgbe->intr_cnt;
5613 5588 }
5614 5589
5615 5590 /*
5616 5591 * Map tx ring interrupts to vectors
5617 5592 */
5618 5593 for (i = 0; i < ixgbe->num_tx_rings; i++) {
5619 5594 ixgbe_map_txring_to_vector(ixgbe, i, vector);
5620 5595 vector = (vector +1) % ixgbe->intr_cnt;
5621 5596 }
5622 5597
5623 5598 return (IXGBE_SUCCESS);
5624 5599 }
5625 5600
5626 5601 /*
5627 5602 * ixgbe_setup_adapter_vector - Setup the adapter interrupt vector(s).
5628 5603 *
5629 5604 * This relies on ring/vector mapping already set up in the
5630 5605 * vect_map[] structures
5631 5606 */
5632 5607 static void
5633 5608 ixgbe_setup_adapter_vector(ixgbe_t *ixgbe)
5634 5609 {
5635 5610 struct ixgbe_hw *hw = &ixgbe->hw;
5636 5611 ixgbe_intr_vector_t *vect; /* vector bitmap */
5637 5612 int r_idx; /* ring index */
5638 5613 int v_idx; /* vector index */
5639 5614 uint32_t hw_index;
5640 5615
5641 5616 /*
5642 5617 * Clear any previous entries
5643 5618 */
5644 5619 switch (hw->mac.type) {
5645 5620 case ixgbe_mac_82598EB:
5646 5621 for (v_idx = 0; v_idx < 25; v_idx++)
5647 5622 IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0);
5648 5623 break;
5649 5624
5650 5625 case ixgbe_mac_82599EB:
5651 5626 case ixgbe_mac_X540:
5652 5627 case ixgbe_mac_X550:
5653 5628 case ixgbe_mac_X550EM_x:
5654 5629 case ixgbe_mac_X550EM_a:
5655 5630 for (v_idx = 0; v_idx < 64; v_idx++)
5656 5631 IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0);
5657 5632 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, 0);
5658 5633 break;
5659 5634
5660 5635 default:
5661 5636 break;
5662 5637 }
5663 5638
5664 5639 /*
5665 5640 * For non MSI-X interrupt, rx rings[0] will use RTxQ[0], and
5666 5641 * tx rings[0] will use RTxQ[1].
5667 5642 */
5668 5643 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
5669 5644 ixgbe_setup_ivar(ixgbe, 0, 0, 0);
5670 5645 ixgbe_setup_ivar(ixgbe, 0, 1, 1);
5671 5646 return;
5672 5647 }
5673 5648
5674 5649 /*
5675 5650 * For MSI-X interrupt, "Other" is always on vector[0].
5676 5651 */
5677 5652 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_OTHER_CAUSES_INDEX, 0, -1);
5678 5653
5679 5654 /*
5680 5655 * For each interrupt vector, populate the IVAR table
5681 5656 */
5682 5657 for (v_idx = 0; v_idx < ixgbe->intr_cnt; v_idx++) {
5683 5658 vect = &ixgbe->vect_map[v_idx];
5684 5659
5685 5660 /*
5686 5661 * For each rx ring bit set
5687 5662 */
5688 5663 r_idx = bt_getlowbit(vect->rx_map, 0,
5689 5664 (ixgbe->num_rx_rings - 1));
5690 5665
5691 5666 while (r_idx >= 0) {
5692 5667 hw_index = ixgbe->rx_rings[r_idx].hw_index;
5693 5668 ixgbe_setup_ivar(ixgbe, hw_index, v_idx, 0);
5694 5669 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1),
5695 5670 (ixgbe->num_rx_rings - 1));
5696 5671 }
5697 5672
5698 5673 /*
5699 5674 * For each tx ring bit set
5700 5675 */
5701 5676 r_idx = bt_getlowbit(vect->tx_map, 0,
5702 5677 (ixgbe->num_tx_rings - 1));
5703 5678
5704 5679 while (r_idx >= 0) {
5705 5680 ixgbe_setup_ivar(ixgbe, r_idx, v_idx, 1);
5706 5681 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1),
5707 5682 (ixgbe->num_tx_rings - 1));
5708 5683 }
5709 5684 }
5710 5685 }
5711 5686
5712 5687 /*
5713 5688 * ixgbe_rem_intr_handlers - Remove the interrupt handlers.
5714 5689 */
5715 5690 static void
5716 5691 ixgbe_rem_intr_handlers(ixgbe_t *ixgbe)
5717 5692 {
5718 5693 int i;
5719 5694 int rc;
5720 5695
5721 5696 for (i = 0; i < ixgbe->intr_cnt; i++) {
5722 5697 rc = ddi_intr_remove_handler(ixgbe->htable[i]);
5723 5698 if (rc != DDI_SUCCESS) {
5724 5699 IXGBE_DEBUGLOG_1(ixgbe,
5725 5700 "Remove intr handler failed: %d", rc);
5726 5701 }
5727 5702 }
5728 5703 }
5729 5704
5730 5705 /*
5731 5706 * ixgbe_rem_intrs - Remove the allocated interrupts.
5732 5707 */
5733 5708 static void
5734 5709 ixgbe_rem_intrs(ixgbe_t *ixgbe)
5735 5710 {
5736 5711 int i;
5737 5712 int rc;
5738 5713
5739 5714 for (i = 0; i < ixgbe->intr_cnt; i++) {
5740 5715 rc = ddi_intr_free(ixgbe->htable[i]);
5741 5716 if (rc != DDI_SUCCESS) {
5742 5717 IXGBE_DEBUGLOG_1(ixgbe,
5743 5718 "Free intr failed: %d", rc);
5744 5719 }
5745 5720 }
5746 5721
5747 5722 kmem_free(ixgbe->htable, ixgbe->intr_size);
5748 5723 ixgbe->htable = NULL;
5749 5724 }
5750 5725
5751 5726 /*
5752 5727 * ixgbe_enable_intrs - Enable all the ddi interrupts.
5753 5728 */
5754 5729 static int
5755 5730 ixgbe_enable_intrs(ixgbe_t *ixgbe)
5756 5731 {
5757 5732 int i;
5758 5733 int rc;
5759 5734
5760 5735 /*
5761 5736 * Enable interrupts
5762 5737 */
5763 5738 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5764 5739 /*
5765 5740 * Call ddi_intr_block_enable() for MSI
5766 5741 */
5767 5742 rc = ddi_intr_block_enable(ixgbe->htable, ixgbe->intr_cnt);
5768 5743 if (rc != DDI_SUCCESS) {
5769 5744 ixgbe_log(ixgbe,
5770 5745 "Enable block intr failed: %d", rc);
5771 5746 return (IXGBE_FAILURE);
5772 5747 }
5773 5748 } else {
5774 5749 /*
5775 5750 * Call ddi_intr_enable() for Legacy/MSI non block enable
5776 5751 */
5777 5752 for (i = 0; i < ixgbe->intr_cnt; i++) {
5778 5753 rc = ddi_intr_enable(ixgbe->htable[i]);
5779 5754 if (rc != DDI_SUCCESS) {
5780 5755 ixgbe_log(ixgbe,
5781 5756 "Enable intr failed: %d", rc);
5782 5757 return (IXGBE_FAILURE);
5783 5758 }
5784 5759 }
5785 5760 }
5786 5761
5787 5762 return (IXGBE_SUCCESS);
5788 5763 }
5789 5764
5790 5765 /*
5791 5766 * ixgbe_disable_intrs - Disable all the interrupts.
5792 5767 */
5793 5768 static int
5794 5769 ixgbe_disable_intrs(ixgbe_t *ixgbe)
5795 5770 {
5796 5771 int i;
5797 5772 int rc;
5798 5773
5799 5774 /*
5800 5775 * Disable all interrupts
5801 5776 */
5802 5777 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5803 5778 rc = ddi_intr_block_disable(ixgbe->htable, ixgbe->intr_cnt);
5804 5779 if (rc != DDI_SUCCESS) {
5805 5780 ixgbe_log(ixgbe,
5806 5781 "Disable block intr failed: %d", rc);
5807 5782 return (IXGBE_FAILURE);
5808 5783 }
5809 5784 } else {
5810 5785 for (i = 0; i < ixgbe->intr_cnt; i++) {
5811 5786 rc = ddi_intr_disable(ixgbe->htable[i]);
5812 5787 if (rc != DDI_SUCCESS) {
5813 5788 ixgbe_log(ixgbe,
5814 5789 "Disable intr failed: %d", rc);
5815 5790 return (IXGBE_FAILURE);
5816 5791 }
5817 5792 }
5818 5793 }
5819 5794
5820 5795 return (IXGBE_SUCCESS);
5821 5796 }
5822 5797
5823 5798 /*
5824 5799 * ixgbe_get_hw_state - Get and save parameters related to adapter hardware.
5825 5800 */
5826 5801 static void
5827 5802 ixgbe_get_hw_state(ixgbe_t *ixgbe)
5828 5803 {
5829 5804 struct ixgbe_hw *hw = &ixgbe->hw;
5830 5805 ixgbe_link_speed speed = 0;
5831 5806 boolean_t link_up = B_FALSE;
5832 5807 uint32_t pcs1g_anlp = 0;
5833 5808
5834 5809 ASSERT(mutex_owned(&ixgbe->gen_lock));
5835 5810 ixgbe->param_lp_1000fdx_cap = 0;
5836 5811 ixgbe->param_lp_100fdx_cap = 0;
5837 5812
5838 5813 /* check for link, don't wait */
5839 5814 (void) ixgbe_check_link(hw, &speed, &link_up, B_FALSE);
5840 5815
5841 5816 /*
5842 5817 * Update the observed Link Partner's capabilities. Not all adapters
5843 5818 * can provide full information on the LP's capable speeds, so we
5844 5819 * provide what we can.
5845 5820 */
5846 5821 if (link_up) {
5847 5822 pcs1g_anlp = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
5848 5823
5849 5824 ixgbe->param_lp_1000fdx_cap =
5850 5825 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0;
5851 5826 ixgbe->param_lp_100fdx_cap =
5852 5827 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0;
5853 5828 }
5854 5829
5855 5830 /*
5856 5831 * Update GLD's notion of the adapter's currently advertised speeds.
5857 5832 * Since the common code doesn't always record the current autonegotiate
5858 5833 * settings in the phy struct for all parts (specifically, adapters with
5859 5834 * SFPs) we first test to see if it is 0, and if so, we fall back to
5860 5835 * using the adapter's speed capabilities which we saved during instance
5861 5836 * init in ixgbe_init_params().
5862 5837 *
5863 5838 * Adapters with SFPs will always be shown as advertising all of their
5864 5839 * supported speeds, and adapters with baseT PHYs (where the phy struct
5865 5840 * is maintained by the common code) will always have a factual view of
5866 5841 * their currently-advertised speeds. In the case of SFPs, this is
5867 5842 * acceptable as we default to advertising all speeds that the adapter
5868 5843 * claims to support, and those properties are immutable; unlike on
5869 5844 * baseT (copper) PHYs, where speeds can be enabled or disabled at will.
5870 5845 */
5871 5846 speed = hw->phy.autoneg_advertised;
5872 5847 if (speed == 0)
5873 5848 speed = ixgbe->speeds_supported;
5874 5849
5875 5850 ixgbe->param_adv_10000fdx_cap =
5876 5851 (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
5877 5852 ixgbe->param_adv_5000fdx_cap =
5878 5853 (speed & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
5879 5854 ixgbe->param_adv_2500fdx_cap =
5880 5855 (speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
5881 5856 ixgbe->param_adv_1000fdx_cap =
5882 5857 (speed & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
5883 5858 ixgbe->param_adv_100fdx_cap =
5884 5859 (speed & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
5885 5860 }
5886 5861
5887 5862 /*
5888 5863 * ixgbe_get_driver_control - Notify that driver is in control of device.
5889 5864 */
5890 5865 static void
5891 5866 ixgbe_get_driver_control(struct ixgbe_hw *hw)
5892 5867 {
5893 5868 uint32_t ctrl_ext;
5894 5869
5895 5870 /*
5896 5871 * Notify firmware that driver is in control of device
5897 5872 */
5898 5873 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5899 5874 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
5900 5875 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5901 5876 }
5902 5877
5903 5878 /*
5904 5879 * ixgbe_release_driver_control - Notify that driver is no longer in control
5905 5880 * of device.
5906 5881 */
5907 5882 static void
5908 5883 ixgbe_release_driver_control(struct ixgbe_hw *hw)
5909 5884 {
5910 5885 uint32_t ctrl_ext;
5911 5886
5912 5887 /*
5913 5888 * Notify firmware that driver is no longer in control of device
5914 5889 */
5915 5890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5916 5891 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
5917 5892 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5918 5893 }
5919 5894
5920 5895 /*
5921 5896 * ixgbe_atomic_reserve - Atomic decrease operation.
5922 5897 */
5923 5898 int
5924 5899 ixgbe_atomic_reserve(uint32_t *count_p, uint32_t n)
5925 5900 {
5926 5901 uint32_t oldval;
5927 5902 uint32_t newval;
5928 5903
5929 5904 /*
5930 5905 * ATOMICALLY
5931 5906 */
5932 5907 do {
5933 5908 oldval = *count_p;
5934 5909 if (oldval < n)
5935 5910 return (-1);
5936 5911 newval = oldval - n;
5937 5912 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5938 5913
5939 5914 return (newval);
5940 5915 }
5941 5916
5942 5917 /*
5943 5918 * ixgbe_mc_table_itr - Traverse the entries in the multicast table.
5944 5919 */
5945 5920 static uint8_t *
5946 5921 ixgbe_mc_table_itr(struct ixgbe_hw *hw, uint8_t **upd_ptr, uint32_t *vmdq)
5947 5922 {
5948 5923 uint8_t *addr = *upd_ptr;
5949 5924 uint8_t *new_ptr;
5950 5925
5951 5926 _NOTE(ARGUNUSED(hw));
5952 5927 _NOTE(ARGUNUSED(vmdq));
5953 5928
5954 5929 new_ptr = addr + IXGBE_ETH_LENGTH_OF_ADDRESS;
5955 5930 *upd_ptr = new_ptr;
5956 5931 return (addr);
5957 5932 }
5958 5933
5959 5934 /*
5960 5935 * FMA support
5961 5936 */
5962 5937 int
5963 5938 ixgbe_check_acc_handle(ddi_acc_handle_t handle)
5964 5939 {
5965 5940 ddi_fm_error_t de;
5966 5941
5967 5942 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5968 5943 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5969 5944 return (de.fme_status);
5970 5945 }
5971 5946
5972 5947 int
5973 5948 ixgbe_check_dma_handle(ddi_dma_handle_t handle)
5974 5949 {
5975 5950 ddi_fm_error_t de;
5976 5951
5977 5952 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5978 5953 return (de.fme_status);
5979 5954 }
5980 5955
5981 5956 /*
5982 5957 * ixgbe_fm_error_cb - The IO fault service error handling callback function.
5983 5958 */
5984 5959 static int
5985 5960 ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5986 5961 {
5987 5962 _NOTE(ARGUNUSED(impl_data));
5988 5963 /*
5989 5964 * as the driver can always deal with an error in any dma or
5990 5965 * access handle, we can just return the fme_status value.
5991 5966 */
5992 5967 pci_ereport_post(dip, err, NULL);
5993 5968 return (err->fme_status);
5994 5969 }
5995 5970
5996 5971 static void
5997 5972 ixgbe_fm_init(ixgbe_t *ixgbe)
5998 5973 {
5999 5974 ddi_iblock_cookie_t iblk;
6000 5975 int fma_dma_flag;
6001 5976
6002 5977 /*
6003 5978 * Only register with IO Fault Services if we have some capability
6004 5979 */
6005 5980 if (ixgbe->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
6006 5981 ixgbe_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
6007 5982 } else {
6008 5983 ixgbe_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
6009 5984 }
6010 5985
6011 5986 if (ixgbe->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
6012 5987 fma_dma_flag = 1;
6013 5988 } else {
6014 5989 fma_dma_flag = 0;
6015 5990 }
6016 5991
6017 5992 ixgbe_set_fma_flags(fma_dma_flag);
6018 5993
6019 5994 if (ixgbe->fm_capabilities) {
6020 5995
6021 5996 /*
6022 5997 * Register capabilities with IO Fault Services
6023 5998 */
6024 5999 ddi_fm_init(ixgbe->dip, &ixgbe->fm_capabilities, &iblk);
6025 6000
6026 6001 /*
6027 6002 * Initialize pci ereport capabilities if ereport capable
6028 6003 */
6029 6004 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
6030 6005 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
6031 6006 pci_ereport_setup(ixgbe->dip);
6032 6007
6033 6008 /*
6034 6009 * Register error callback if error callback capable
6035 6010 */
6036 6011 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
6037 6012 ddi_fm_handler_register(ixgbe->dip,
6038 6013 ixgbe_fm_error_cb, (void*) ixgbe);
6039 6014 }
6040 6015 }
6041 6016
6042 6017 static void
6043 6018 ixgbe_fm_fini(ixgbe_t *ixgbe)
6044 6019 {
6045 6020 /*
6046 6021 * Only unregister FMA capabilities if they are registered
6047 6022 */
6048 6023 if (ixgbe->fm_capabilities) {
6049 6024
6050 6025 /*
6051 6026 * Release any resources allocated by pci_ereport_setup()
6052 6027 */
6053 6028 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
6054 6029 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
6055 6030 pci_ereport_teardown(ixgbe->dip);
6056 6031
6057 6032 /*
6058 6033 * Un-register error callback if error callback capable
6059 6034 */
6060 6035 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
6061 6036 ddi_fm_handler_unregister(ixgbe->dip);
6062 6037
6063 6038 /*
6064 6039 * Unregister from IO Fault Service
6065 6040 */
6066 6041 ddi_fm_fini(ixgbe->dip);
6067 6042 }
6068 6043 }
6069 6044
6070 6045 void
6071 6046 ixgbe_fm_ereport(ixgbe_t *ixgbe, char *detail)
6072 6047 {
6073 6048 uint64_t ena;
6074 6049 char buf[FM_MAX_CLASS];
6075 6050
6076 6051 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
6077 6052 ena = fm_ena_generate(0, FM_ENA_FMT1);
6078 6053 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities)) {
6079 6054 ddi_fm_ereport_post(ixgbe->dip, buf, ena, DDI_NOSLEEP,
6080 6055 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
6081 6056 }
6082 6057 }
6083 6058
6084 6059 static int
6085 6060 ixgbe_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
6086 6061 {
6087 6062 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)rh;
6088 6063
6089 6064 mutex_enter(&rx_ring->rx_lock);
6090 6065 rx_ring->ring_gen_num = mr_gen_num;
6091 6066 mutex_exit(&rx_ring->rx_lock);
6092 6067 return (0);
6093 6068 }
6094 6069
6095 6070 /*
6096 6071 * Get the global ring index by a ring index within a group.
6097 6072 */
6098 6073 static int
6099 6074 ixgbe_get_rx_ring_index(ixgbe_t *ixgbe, int gindex, int rindex)
6100 6075 {
6101 6076 ixgbe_rx_ring_t *rx_ring;
6102 6077 int i;
6103 6078
6104 6079 for (i = 0; i < ixgbe->num_rx_rings; i++) {
6105 6080 rx_ring = &ixgbe->rx_rings[i];
6106 6081 if (rx_ring->group_index == gindex)
6107 6082 rindex--;
6108 6083 if (rindex < 0)
6109 6084 return (i);
6110 6085 }
6111 6086
6112 6087 return (-1);
6113 6088 }
6114 6089
6115 6090 /*
6116 6091 * Callback funtion for MAC layer to register all rings.
6117 6092 */
6118 6093 /* ARGSUSED */
6119 6094 void
6120 6095 ixgbe_fill_ring(void *arg, mac_ring_type_t rtype, const int group_index,
6121 6096 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
6122 6097 {
6123 6098 ixgbe_t *ixgbe = (ixgbe_t *)arg;
6124 6099 mac_intr_t *mintr = &infop->mri_intr;
6125 6100
6126 6101 switch (rtype) {
6127 6102 case MAC_RING_TYPE_RX: {
6128 6103 /*
6129 6104 * 'index' is the ring index within the group.
6130 6105 * Need to get the global ring index by searching in groups.
6131 6106 */
6132 6107 int global_ring_index = ixgbe_get_rx_ring_index(
6133 6108 ixgbe, group_index, ring_index);
6134 6109
6135 6110 ASSERT(global_ring_index >= 0);
6136 6111
6137 6112 ixgbe_rx_ring_t *rx_ring = &ixgbe->rx_rings[global_ring_index];
6138 6113 rx_ring->ring_handle = rh;
6139 6114
6140 6115 infop->mri_driver = (mac_ring_driver_t)rx_ring;
6141 6116 infop->mri_start = ixgbe_ring_start;
6142 6117 infop->mri_stop = NULL;
6143 6118 infop->mri_poll = ixgbe_ring_rx_poll;
6144 6119 infop->mri_stat = ixgbe_rx_ring_stat;
6145 6120
6146 6121 mintr->mi_handle = (mac_intr_handle_t)rx_ring;
6147 6122 mintr->mi_enable = ixgbe_rx_ring_intr_enable;
6148 6123 mintr->mi_disable = ixgbe_rx_ring_intr_disable;
6149 6124 if (ixgbe->intr_type &
6150 6125 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
6151 6126 mintr->mi_ddi_handle =
6152 6127 ixgbe->htable[rx_ring->intr_vector];
6153 6128 }
6154 6129
6155 6130 break;
6156 6131 }
6157 6132 case MAC_RING_TYPE_TX: {
6158 6133 ASSERT(group_index == -1);
6159 6134 ASSERT(ring_index < ixgbe->num_tx_rings);
6160 6135
6161 6136 ixgbe_tx_ring_t *tx_ring = &ixgbe->tx_rings[ring_index];
6162 6137 tx_ring->ring_handle = rh;
6163 6138
6164 6139 infop->mri_driver = (mac_ring_driver_t)tx_ring;
6165 6140 infop->mri_start = NULL;
6166 6141 infop->mri_stop = NULL;
6167 6142 infop->mri_tx = ixgbe_ring_tx;
6168 6143 infop->mri_stat = ixgbe_tx_ring_stat;
6169 6144 if (ixgbe->intr_type &
6170 6145 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
6171 6146 mintr->mi_ddi_handle =
6172 6147 ixgbe->htable[tx_ring->intr_vector];
6173 6148 }
6174 6149 break;
6175 6150 }
6176 6151 default:
6177 6152 break;
6178 6153 }
6179 6154 }
6180 6155
6181 6156 /*
6182 6157 * Callback funtion for MAC layer to register all groups.
6183 6158 */
6184 6159 void
6185 6160 ixgbe_fill_group(void *arg, mac_ring_type_t rtype, const int index,
6186 6161 mac_group_info_t *infop, mac_group_handle_t gh)
6187 6162 {
6188 6163 ixgbe_t *ixgbe = (ixgbe_t *)arg;
6189 6164
6190 6165 switch (rtype) {
6191 6166 case MAC_RING_TYPE_RX: {
6192 6167 ixgbe_rx_group_t *rx_group;
6193 6168
6194 6169 rx_group = &ixgbe->rx_groups[index];
6195 6170 rx_group->group_handle = gh;
6196 6171
6197 6172 infop->mgi_driver = (mac_group_driver_t)rx_group;
6198 6173 infop->mgi_start = NULL;
6199 6174 infop->mgi_stop = NULL;
6200 6175 infop->mgi_addmac = ixgbe_addmac;
6201 6176 infop->mgi_remmac = ixgbe_remmac;
6202 6177 infop->mgi_count = (ixgbe->num_rx_rings / ixgbe->num_rx_groups);
6203 6178
6204 6179 break;
6205 6180 }
6206 6181 case MAC_RING_TYPE_TX:
6207 6182 break;
6208 6183 default:
6209 6184 break;
6210 6185 }
6211 6186 }
6212 6187
6213 6188 /*
6214 6189 * Enable interrupt on the specificed rx ring.
6215 6190 */
6216 6191 int
6217 6192 ixgbe_rx_ring_intr_enable(mac_intr_handle_t intrh)
6218 6193 {
6219 6194 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh;
6220 6195 ixgbe_t *ixgbe = rx_ring->ixgbe;
6221 6196 int r_idx = rx_ring->index;
6222 6197 int hw_r_idx = rx_ring->hw_index;
6223 6198 int v_idx = rx_ring->intr_vector;
6224 6199
6225 6200 mutex_enter(&ixgbe->gen_lock);
6226 6201 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
6227 6202 mutex_exit(&ixgbe->gen_lock);
6228 6203 /*
6229 6204 * Simply return 0.
6230 6205 * Interrupts are being adjusted. ixgbe_intr_adjust()
6231 6206 * will eventually re-enable the interrupt when it's
6232 6207 * done with the adjustment.
6233 6208 */
6234 6209 return (0);
6235 6210 }
6236 6211
6237 6212 /*
6238 6213 * To enable interrupt by setting the VAL bit of given interrupt
6239 6214 * vector allocation register (IVAR).
6240 6215 */
6241 6216 ixgbe_enable_ivar(ixgbe, hw_r_idx, 0);
6242 6217
6243 6218 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
6244 6219
6245 6220 /*
6246 6221 * Trigger a Rx interrupt on this ring
6247 6222 */
6248 6223 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_EICS, (1 << v_idx));
6249 6224 IXGBE_WRITE_FLUSH(&ixgbe->hw);
6250 6225
6251 6226 mutex_exit(&ixgbe->gen_lock);
6252 6227
6253 6228 return (0);
6254 6229 }
6255 6230
6256 6231 /*
6257 6232 * Disable interrupt on the specificed rx ring.
6258 6233 */
6259 6234 int
6260 6235 ixgbe_rx_ring_intr_disable(mac_intr_handle_t intrh)
6261 6236 {
6262 6237 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh;
6263 6238 ixgbe_t *ixgbe = rx_ring->ixgbe;
6264 6239 int r_idx = rx_ring->index;
6265 6240 int hw_r_idx = rx_ring->hw_index;
6266 6241 int v_idx = rx_ring->intr_vector;
6267 6242
6268 6243 mutex_enter(&ixgbe->gen_lock);
6269 6244 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
6270 6245 mutex_exit(&ixgbe->gen_lock);
6271 6246 /*
6272 6247 * Simply return 0.
6273 6248 * In the rare case where an interrupt is being
6274 6249 * disabled while interrupts are being adjusted,
6275 6250 * we don't fail the operation. No interrupts will
6276 6251 * be generated while they are adjusted, and
6277 6252 * ixgbe_intr_adjust() will cause the interrupts
6278 6253 * to be re-enabled once it completes. Note that
6279 6254 * in this case, packets may be delivered to the
6280 6255 * stack via interrupts before xgbe_rx_ring_intr_enable()
6281 6256 * is called again. This is acceptable since interrupt
6282 6257 * adjustment is infrequent, and the stack will be
6283 6258 * able to handle these packets.
6284 6259 */
6285 6260 return (0);
6286 6261 }
6287 6262
6288 6263 /*
6289 6264 * To disable interrupt by clearing the VAL bit of given interrupt
6290 6265 * vector allocation register (IVAR).
6291 6266 */
6292 6267 ixgbe_disable_ivar(ixgbe, hw_r_idx, 0);
6293 6268
6294 6269 BT_CLEAR(ixgbe->vect_map[v_idx].rx_map, r_idx);
6295 6270
6296 6271 mutex_exit(&ixgbe->gen_lock);
6297 6272
6298 6273 return (0);
6299 6274 }
6300 6275
6301 6276 /*
6302 6277 * Add a mac address.
6303 6278 */
6304 6279 static int
6305 6280 ixgbe_addmac(void *arg, const uint8_t *mac_addr)
6306 6281 {
6307 6282 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg;
6308 6283 ixgbe_t *ixgbe = rx_group->ixgbe;
6309 6284 struct ixgbe_hw *hw = &ixgbe->hw;
6310 6285 int slot, i;
6311 6286
6312 6287 mutex_enter(&ixgbe->gen_lock);
6313 6288
6314 6289 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
6315 6290 mutex_exit(&ixgbe->gen_lock);
6316 6291 return (ECANCELED);
6317 6292 }
6318 6293
6319 6294 if (ixgbe->unicst_avail == 0) {
6320 6295 /* no slots available */
6321 6296 mutex_exit(&ixgbe->gen_lock);
6322 6297 return (ENOSPC);
6323 6298 }
6324 6299
6325 6300 /*
6326 6301 * The first ixgbe->num_rx_groups slots are reserved for each respective
6327 6302 * group. The rest slots are shared by all groups. While adding a
6328 6303 * MAC address, reserved slots are firstly checked then the shared
6329 6304 * slots are searched.
6330 6305 */
6331 6306 slot = -1;
6332 6307 if (ixgbe->unicst_addr[rx_group->index].mac.set == 1) {
6333 6308 for (i = ixgbe->num_rx_groups; i < ixgbe->unicst_total; i++) {
6334 6309 if (ixgbe->unicst_addr[i].mac.set == 0) {
6335 6310 slot = i;
6336 6311 break;
6337 6312 }
6338 6313 }
6339 6314 } else {
6340 6315 slot = rx_group->index;
6341 6316 }
6342 6317
6343 6318 if (slot == -1) {
6344 6319 /* no slots available */
6345 6320 mutex_exit(&ixgbe->gen_lock);
6346 6321 return (ENOSPC);
6347 6322 }
6348 6323
6349 6324 bcopy(mac_addr, ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
6350 6325 (void) ixgbe_set_rar(hw, slot, ixgbe->unicst_addr[slot].mac.addr,
6351 6326 rx_group->index, IXGBE_RAH_AV);
6352 6327 ixgbe->unicst_addr[slot].mac.set = 1;
6353 6328 ixgbe->unicst_addr[slot].mac.group_index = rx_group->index;
6354 6329 ixgbe->unicst_avail--;
6355 6330
6356 6331 mutex_exit(&ixgbe->gen_lock);
6357 6332
6358 6333 return (0);
6359 6334 }
6360 6335
6361 6336 /*
6362 6337 * Remove a mac address.
6363 6338 */
6364 6339 static int
6365 6340 ixgbe_remmac(void *arg, const uint8_t *mac_addr)
6366 6341 {
6367 6342 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg;
6368 6343 ixgbe_t *ixgbe = rx_group->ixgbe;
6369 6344 struct ixgbe_hw *hw = &ixgbe->hw;
6370 6345 int slot;
6371 6346
6372 6347 mutex_enter(&ixgbe->gen_lock);
6373 6348
6374 6349 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
6375 6350 mutex_exit(&ixgbe->gen_lock);
6376 6351 return (ECANCELED);
6377 6352 }
6378 6353
6379 6354 slot = ixgbe_unicst_find(ixgbe, mac_addr);
6380 6355 if (slot == -1) {
6381 6356 mutex_exit(&ixgbe->gen_lock);
6382 6357 return (EINVAL);
6383 6358 }
6384 6359
6385 6360 if (ixgbe->unicst_addr[slot].mac.set == 0) {
6386 6361 mutex_exit(&ixgbe->gen_lock);
6387 6362 return (EINVAL);
6388 6363 }
6389 6364
6390 6365 bzero(ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
6391 6366 (void) ixgbe_clear_rar(hw, slot);
6392 6367 ixgbe->unicst_addr[slot].mac.set = 0;
6393 6368 ixgbe->unicst_avail++;
6394 6369
6395 6370 mutex_exit(&ixgbe->gen_lock);
6396 6371
6397 6372 return (0);
6398 6373 }
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