Print this page
12011 ixgbe reports incorrect MAC_STAT_NORCVBUF
Change-Id: Ia71b5669b2bc8f6256a84b0b9c673153f327f5ab
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/common/io/ixgbe/ixgbe_stat.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_stat.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
↓ open down ↓ |
19 lines elided |
↑ open up ↑ |
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29 29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 - * Copyright (c) 2017, Joyent, Inc.
30 + * Copyright 2019 Joyent, Inc.
31 31 */
32 32
33 33 #include "ixgbe_sw.h"
34 34
35 35 /*
36 + * The 82598 controller lacks a high/low register for the various
37 + * octet counters, but the common code also lacks a definition for
38 + * these older registers. In these cases, the high register address
39 + * maps to the appropriate address in the 82598 controller.
40 + */
41 +#define IXGBE_TOR IXGBE_TORH
42 +#define IXGBE_GOTC IXGBE_GOTCH
43 +#define IXGBE_GORC IXGBE_GORCH
44 +
45 +/*
46 + * Read total octets received.
47 + */
48 +static uint64_t
49 +ixgbe_read_tor_value(const struct ixgbe_hw *hw)
50 +{
51 + uint64_t tor = 0;
52 + uint64_t hi = 0, lo = 0;
53 +
54 + switch (hw->mac.type) {
55 + case ixgbe_mac_82598EB:
56 + tor = IXGBE_READ_REG(hw, IXGBE_TOR);
57 + break;
58 +
59 + default:
60 + lo = IXGBE_READ_REG(hw, IXGBE_TORL);
61 + hi = IXGBE_READ_REG(hw, IXGBE_TORH) & 0xF;
62 + tor = (hi << 32) + lo;
63 + break;
64 + }
65 +
66 + return (tor);
67 +}
68 +
69 +/*
70 + * Read queue octets received.
71 + */
72 +static uint64_t
73 +ixgbe_read_qor_value(const struct ixgbe_hw *hw)
74 +{
75 + uint64_t qor = 0;
76 + uint64_t hi = 0, lo = 0;
77 +
78 + switch (hw->mac.type) {
79 + case ixgbe_mac_82598EB:
80 + qor = IXGBE_READ_REG(hw, IXGBE_QBRC(0));
81 + break;
82 +
83 + default:
84 + lo = IXGBE_READ_REG(hw, IXGBE_QBRC_L(0));
85 + hi = IXGBE_READ_REG(hw, IXGBE_QBRC_H(0)) & 0xF;
86 + qor = (hi << 32) + lo;
87 + break;
88 + }
89 +
90 + return (qor);
91 +}
92 +
93 +/*
94 + * Read queue octets transmitted.
95 + */
96 +static uint64_t
97 +ixgbe_read_qot_value(const struct ixgbe_hw *hw)
98 +{
99 + uint64_t qot = 0;
100 + uint64_t hi = 0, lo = 0;
101 +
102 + switch (hw->mac.type) {
103 + case ixgbe_mac_82598EB:
104 + qot = IXGBE_READ_REG(hw, IXGBE_QBTC(0));
105 + break;
106 +
107 + default:
108 + lo = IXGBE_READ_REG(hw, IXGBE_QBTC_L(0));
109 + hi = IXGBE_READ_REG(hw, IXGBE_QBTC_H(0)) & 0xF;
110 + qot = (hi << 32) + lo;
111 + break;
112 + }
113 +
114 + return (qot);
115 +}
116 +
117 +/*
118 + * Read good octets transmitted.
119 + */
120 +static uint64_t
121 +ixgbe_read_got_value(const struct ixgbe_hw *hw)
122 +{
123 + uint64_t got = 0;
124 + uint64_t hi = 0, lo = 0;
125 +
126 + switch (hw->mac.type) {
127 + case ixgbe_mac_82598EB:
128 + got = IXGBE_READ_REG(hw, IXGBE_GOTC);
129 + break;
130 +
131 + default:
132 + lo = IXGBE_READ_REG(hw, IXGBE_GOTCL);
133 + hi = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
134 + got = (hi << 32) + lo;
135 + break;
136 + }
137 +
138 + return (got);
139 +}
140 +
141 +/*
142 + * Read good octets received.
143 + */
144 +static uint64_t
145 +ixgbe_read_gor_value(const struct ixgbe_hw *hw)
146 +{
147 + uint64_t gor = 0;
148 + uint64_t hi = 0, lo = 0;
149 +
150 + switch (hw->mac.type) {
151 + case ixgbe_mac_82598EB:
152 + gor = IXGBE_READ_REG(hw, IXGBE_GORC);
153 + break;
154 +
155 + default:
156 + lo = IXGBE_READ_REG(hw, IXGBE_GORCL);
157 + hi = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
158 + gor = (hi << 32) + lo;
159 + break;
160 + }
161 +
162 + return (gor);
163 +}
164 +
165 +/*
36 166 * Update driver private statistics.
37 167 */
38 168 static int
39 169 ixgbe_update_stats(kstat_t *ks, int rw)
40 170 {
41 171 ixgbe_t *ixgbe;
42 172 struct ixgbe_hw *hw;
43 173 ixgbe_stat_t *ixgbe_ks;
44 174 int i;
45 175
46 176 if (rw == KSTAT_WRITE)
47 177 return (EACCES);
48 178
49 179 ixgbe = (ixgbe_t *)ks->ks_private;
50 180 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
51 181 hw = &ixgbe->hw;
52 182
53 183 mutex_enter(&ixgbe->gen_lock);
54 184
55 185 /*
56 186 * Basic information
57 187 */
58 188 ixgbe_ks->link_speed.value.ui64 = ixgbe->link_speed;
59 189 ixgbe_ks->reset_count.value.ui64 = ixgbe->reset_count;
60 190 ixgbe_ks->lroc.value.ui64 = ixgbe->lro_pkt_count;
61 191
62 192 ixgbe_ks->rx_frame_error.value.ui64 = 0;
63 193 ixgbe_ks->rx_cksum_error.value.ui64 = 0;
64 194 ixgbe_ks->rx_exceed_pkt.value.ui64 = 0;
65 195 for (i = 0; i < ixgbe->num_rx_rings; i++) {
66 196 ixgbe_ks->rx_frame_error.value.ui64 +=
67 197 ixgbe->rx_rings[i].stat_frame_error;
68 198 ixgbe_ks->rx_cksum_error.value.ui64 +=
69 199 ixgbe->rx_rings[i].stat_cksum_error;
70 200 ixgbe_ks->rx_exceed_pkt.value.ui64 +=
71 201 ixgbe->rx_rings[i].stat_exceed_pkt;
72 202 }
73 203
74 204 ixgbe_ks->tx_overload.value.ui64 = 0;
75 205 ixgbe_ks->tx_fail_no_tbd.value.ui64 = 0;
76 206 ixgbe_ks->tx_fail_no_tcb.value.ui64 = 0;
77 207 ixgbe_ks->tx_fail_dma_bind.value.ui64 = 0;
78 208 ixgbe_ks->tx_reschedule.value.ui64 = 0;
79 209 ixgbe_ks->tx_break_tbd_limit.value.ui64 = 0;
80 210 ixgbe_ks->tx_lso_header_fail.value.ui64 = 0;
81 211 for (i = 0; i < ixgbe->num_tx_rings; i++) {
82 212 ixgbe_ks->tx_overload.value.ui64 +=
83 213 ixgbe->tx_rings[i].stat_overload;
84 214 ixgbe_ks->tx_fail_no_tbd.value.ui64 +=
85 215 ixgbe->tx_rings[i].stat_fail_no_tbd;
86 216 ixgbe_ks->tx_fail_no_tcb.value.ui64 +=
87 217 ixgbe->tx_rings[i].stat_fail_no_tcb;
88 218 ixgbe_ks->tx_fail_dma_bind.value.ui64 +=
89 219 ixgbe->tx_rings[i].stat_fail_dma_bind;
90 220 ixgbe_ks->tx_reschedule.value.ui64 +=
↓ open down ↓ |
45 lines elided |
↑ open up ↑ |
91 221 ixgbe->tx_rings[i].stat_reschedule;
92 222 ixgbe_ks->tx_break_tbd_limit.value.ui64 +=
93 223 ixgbe->tx_rings[i].stat_break_tbd_limit;
94 224 ixgbe_ks->tx_lso_header_fail.value.ui64 +=
95 225 ixgbe->tx_rings[i].stat_lso_header_fail;
96 226 }
97 227
98 228 /*
99 229 * Hardware calculated statistics.
100 230 */
101 - ixgbe_ks->gprc.value.ui64 = 0;
102 - ixgbe_ks->gptc.value.ui64 = 0;
103 - ixgbe_ks->tor.value.ui64 = 0;
104 - ixgbe_ks->tot.value.ui64 = 0;
105 - for (i = 0; i < 16; i++) {
106 - ixgbe_ks->qprc[i].value.ui64 +=
107 - IXGBE_READ_REG(hw, IXGBE_QPRC(i));
108 - ixgbe_ks->gprc.value.ui64 += ixgbe_ks->qprc[i].value.ui64;
109 - ixgbe_ks->qptc[i].value.ui64 +=
110 - IXGBE_READ_REG(hw, IXGBE_QPTC(i));
111 - ixgbe_ks->gptc.value.ui64 += ixgbe_ks->qptc[i].value.ui64;
112 - ixgbe_ks->qbrc[i].value.ui64 +=
113 - IXGBE_READ_REG(hw, IXGBE_QBRC(i));
114 - ixgbe_ks->tor.value.ui64 += ixgbe_ks->qbrc[i].value.ui64;
115 - switch (hw->mac.type) {
116 - case ixgbe_mac_82598EB:
117 - ixgbe_ks->qbtc[i].value.ui64 +=
118 - IXGBE_READ_REG(hw, IXGBE_QBTC(i));
119 - break;
231 + ixgbe_ks->gprc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_GPRC);
232 + ixgbe_ks->gptc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_GPTC);
233 + ixgbe_ks->gor.value.ui64 += ixgbe_read_gor_value(hw);
234 + ixgbe_ks->got.value.ui64 += ixgbe_read_got_value(hw);
235 + ixgbe_ks->qpr.value.ui64 += IXGBE_READ_REG(hw, IXGBE_QPRC(0));
236 + ixgbe_ks->qpt.value.ui64 += IXGBE_READ_REG(hw, IXGBE_QPTC(0));
237 + ixgbe_ks->qor.value.ui64 += ixgbe_read_qor_value(hw);
238 + ixgbe_ks->qot.value.ui64 += ixgbe_read_qot_value(hw);
239 + ixgbe_ks->tor.value.ui64 += ixgbe_read_tor_value(hw);
240 + ixgbe_ks->tot.value.ui64 = ixgbe_ks->got.value.ui64;
120 241
121 - case ixgbe_mac_82599EB:
122 - case ixgbe_mac_X540:
123 - case ixgbe_mac_X550:
124 - case ixgbe_mac_X550EM_x:
125 - case ixgbe_mac_X550EM_a:
126 - ixgbe_ks->qbtc[i].value.ui64 +=
127 - IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
128 - ixgbe_ks->qbtc[i].value.ui64 +=
129 - ((uint64_t)((IXGBE_READ_REG(hw,
130 - IXGBE_QBTC_H(i))) & 0xF) << 32);
131 - break;
132 -
133 - default:
134 - break;
135 - }
136 - ixgbe_ks->tot.value.ui64 += ixgbe_ks->qbtc[i].value.ui64;
137 - }
138 - /*
139 - * This is a Workaround:
140 - * Currently h/w GORCH, GOTCH, TORH registers are not
141 - * correctly implemented. We found that the values in
142 - * these registers are same as those in corresponding
143 - * *L registers (i.e. GORCL, GOTCL, and TORL). Here the
144 - * gor and got stat data will not be retrieved through
145 - * GORC{H/L} and GOTC{H/L} registers but be obtained by
146 - * simply assigning tor/tot stat data, so the gor/got
147 - * stat data will not be accurate.
148 - */
149 - ixgbe_ks->gor.value.ui64 = ixgbe_ks->tor.value.ui64;
150 - ixgbe_ks->got.value.ui64 = ixgbe_ks->tot.value.ui64;
151 -
152 242 ixgbe_ks->prc64.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC64);
153 243 ixgbe_ks->prc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC127);
154 244 ixgbe_ks->prc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC255);
155 245 ixgbe_ks->prc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC511);
156 246 ixgbe_ks->prc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC1023);
157 247 ixgbe_ks->prc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC1522);
158 248 ixgbe_ks->ptc64.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC64);
159 249 ixgbe_ks->ptc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC127);
160 250 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
161 251 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
162 252 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
163 253 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
164 254
165 255 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
166 256 for (i = 0; i < 8; i++)
167 257 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
168 258 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
169 259 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
170 260 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
171 261 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
172 262 switch (hw->mac.type) {
173 263 case ixgbe_mac_82598EB:
174 264 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
175 265 IXGBE_LXONRXC);
176 266 break;
177 267
178 268 case ixgbe_mac_82599EB:
179 269 case ixgbe_mac_X540:
180 270 case ixgbe_mac_X550:
181 271 case ixgbe_mac_X550EM_x:
182 272 case ixgbe_mac_X550EM_a:
183 273 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
184 274 IXGBE_LXONRXCNT);
185 275 break;
186 276
187 277 default:
188 278 break;
189 279 }
190 280 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
191 281 switch (hw->mac.type) {
192 282 case ixgbe_mac_82598EB:
193 283 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
194 284 IXGBE_LXOFFRXC);
195 285 break;
196 286
197 287 case ixgbe_mac_82599EB:
198 288 case ixgbe_mac_X540:
199 289 case ixgbe_mac_X550:
200 290 case ixgbe_mac_X550EM_x:
201 291 case ixgbe_mac_X550EM_a:
202 292 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
203 293 IXGBE_LXOFFRXCNT);
204 294 break;
205 295
206 296 default:
207 297 break;
208 298 }
209 299 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
210 300 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
211 301 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
212 302 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
213 303
214 304 mutex_exit(&ixgbe->gen_lock);
215 305
216 306 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
217 307 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
218 308
219 309 return (0);
220 310 }
221 311
222 312 /*
223 313 * Create and initialize the driver private statistics.
224 314 */
225 315 int
226 316 ixgbe_init_stats(ixgbe_t *ixgbe)
227 317 {
228 318 kstat_t *ks;
229 319 ixgbe_stat_t *ixgbe_ks;
230 320
231 321 /*
232 322 * Create and init kstat
233 323 */
234 324 ks = kstat_create(MODULE_NAME, ddi_get_instance(ixgbe->dip),
235 325 "statistics", "net", KSTAT_TYPE_NAMED,
236 326 sizeof (ixgbe_stat_t) / sizeof (kstat_named_t), 0);
237 327
238 328 if (ks == NULL) {
239 329 ixgbe_error(ixgbe,
240 330 "Could not create kernel statistics");
241 331 return (IXGBE_FAILURE);
242 332 }
243 333
244 334 ixgbe->ixgbe_ks = ks;
245 335
246 336 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
247 337
248 338 /*
249 339 * Initialize all the statistics.
250 340 */
251 341 kstat_named_init(&ixgbe_ks->link_speed, "link_speed",
252 342 KSTAT_DATA_UINT64);
253 343 kstat_named_init(&ixgbe_ks->reset_count, "reset_count",
254 344 KSTAT_DATA_UINT64);
255 345
256 346 kstat_named_init(&ixgbe_ks->rx_frame_error, "rx_frame_error",
257 347 KSTAT_DATA_UINT64);
258 348 kstat_named_init(&ixgbe_ks->rx_cksum_error, "rx_cksum_error",
259 349 KSTAT_DATA_UINT64);
260 350 kstat_named_init(&ixgbe_ks->rx_exceed_pkt, "rx_exceed_pkt",
261 351 KSTAT_DATA_UINT64);
262 352 kstat_named_init(&ixgbe_ks->tx_overload, "tx_overload",
263 353 KSTAT_DATA_UINT64);
264 354 kstat_named_init(&ixgbe_ks->tx_fail_no_tbd, "tx_fail_no_tbd",
265 355 KSTAT_DATA_UINT64);
266 356 kstat_named_init(&ixgbe_ks->tx_fail_no_tcb, "tx_fail_no_tcb",
267 357 KSTAT_DATA_UINT64);
268 358 kstat_named_init(&ixgbe_ks->tx_fail_dma_bind, "tx_fail_dma_bind",
269 359 KSTAT_DATA_UINT64);
270 360 kstat_named_init(&ixgbe_ks->tx_reschedule, "tx_reschedule",
271 361 KSTAT_DATA_UINT64);
272 362 kstat_named_init(&ixgbe_ks->tx_break_tbd_limit, "tx_break_tbd_limit",
273 363 KSTAT_DATA_UINT64);
274 364 kstat_named_init(&ixgbe_ks->tx_lso_header_fail, "tx_lso_header_fail",
↓ open down ↓ |
113 lines elided |
↑ open up ↑ |
275 365 KSTAT_DATA_UINT64);
276 366
277 367 kstat_named_init(&ixgbe_ks->gprc, "good_pkts_recvd",
278 368 KSTAT_DATA_UINT64);
279 369 kstat_named_init(&ixgbe_ks->gptc, "good_pkts_xmitd",
280 370 KSTAT_DATA_UINT64);
281 371 kstat_named_init(&ixgbe_ks->gor, "good_octets_recvd",
282 372 KSTAT_DATA_UINT64);
283 373 kstat_named_init(&ixgbe_ks->got, "good_octets_xmitd",
284 374 KSTAT_DATA_UINT64);
375 + kstat_named_init(&ixgbe_ks->qor, "queue_octets_recvd",
376 + KSTAT_DATA_UINT64);
377 + kstat_named_init(&ixgbe_ks->qot, "queue_octets_xmitd",
378 + KSTAT_DATA_UINT64);
379 + kstat_named_init(&ixgbe_ks->qpr, "queue_pkts_recvd",
380 + KSTAT_DATA_UINT64);
381 + kstat_named_init(&ixgbe_ks->qpt, "queue_pkts_xmitd",
382 + KSTAT_DATA_UINT64);
285 383 kstat_named_init(&ixgbe_ks->prc64, "pkts_recvd_( 64b)",
286 384 KSTAT_DATA_UINT64);
287 385 kstat_named_init(&ixgbe_ks->prc127, "pkts_recvd_( 65- 127b)",
288 386 KSTAT_DATA_UINT64);
289 387 kstat_named_init(&ixgbe_ks->prc255, "pkts_recvd_( 127- 255b)",
290 388 KSTAT_DATA_UINT64);
291 389 kstat_named_init(&ixgbe_ks->prc511, "pkts_recvd_( 256- 511b)",
292 390 KSTAT_DATA_UINT64);
293 391 kstat_named_init(&ixgbe_ks->prc1023, "pkts_recvd_( 511-1023b)",
294 392 KSTAT_DATA_UINT64);
295 393 kstat_named_init(&ixgbe_ks->prc1522, "pkts_recvd_(1024-1522b)",
296 394 KSTAT_DATA_UINT64);
297 395 kstat_named_init(&ixgbe_ks->ptc64, "pkts_xmitd_( 64b)",
298 396 KSTAT_DATA_UINT64);
299 397 kstat_named_init(&ixgbe_ks->ptc127, "pkts_xmitd_( 65- 127b)",
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
300 398 KSTAT_DATA_UINT64);
301 399 kstat_named_init(&ixgbe_ks->ptc255, "pkts_xmitd_( 128- 255b)",
302 400 KSTAT_DATA_UINT64);
303 401 kstat_named_init(&ixgbe_ks->ptc511, "pkts_xmitd_( 255- 511b)",
304 402 KSTAT_DATA_UINT64);
305 403 kstat_named_init(&ixgbe_ks->ptc1023, "pkts_xmitd_( 512-1023b)",
306 404 KSTAT_DATA_UINT64);
307 405 kstat_named_init(&ixgbe_ks->ptc1522, "pkts_xmitd_(1024-1522b)",
308 406 KSTAT_DATA_UINT64);
309 407
310 - kstat_named_init(&ixgbe_ks->qprc[0], "queue_pkts_recvd [ 0]",
311 - KSTAT_DATA_UINT64);
312 - kstat_named_init(&ixgbe_ks->qprc[1], "queue_pkts_recvd [ 1]",
313 - KSTAT_DATA_UINT64);
314 - kstat_named_init(&ixgbe_ks->qprc[2], "queue_pkts_recvd [ 2]",
315 - KSTAT_DATA_UINT64);
316 - kstat_named_init(&ixgbe_ks->qprc[3], "queue_pkts_recvd [ 3]",
317 - KSTAT_DATA_UINT64);
318 - kstat_named_init(&ixgbe_ks->qprc[4], "queue_pkts_recvd [ 4]",
319 - KSTAT_DATA_UINT64);
320 - kstat_named_init(&ixgbe_ks->qprc[5], "queue_pkts_recvd [ 5]",
321 - KSTAT_DATA_UINT64);
322 - kstat_named_init(&ixgbe_ks->qprc[6], "queue_pkts_recvd [ 6]",
323 - KSTAT_DATA_UINT64);
324 - kstat_named_init(&ixgbe_ks->qprc[7], "queue_pkts_recvd [ 7]",
325 - KSTAT_DATA_UINT64);
326 - kstat_named_init(&ixgbe_ks->qprc[8], "queue_pkts_recvd [ 8]",
327 - KSTAT_DATA_UINT64);
328 - kstat_named_init(&ixgbe_ks->qprc[9], "queue_pkts_recvd [ 9]",
329 - KSTAT_DATA_UINT64);
330 - kstat_named_init(&ixgbe_ks->qprc[10], "queue_pkts_recvd [10]",
331 - KSTAT_DATA_UINT64);
332 - kstat_named_init(&ixgbe_ks->qprc[11], "queue_pkts_recvd [11]",
333 - KSTAT_DATA_UINT64);
334 - kstat_named_init(&ixgbe_ks->qprc[12], "queue_pkts_recvd [12]",
335 - KSTAT_DATA_UINT64);
336 - kstat_named_init(&ixgbe_ks->qprc[13], "queue_pkts_recvd [13]",
337 - KSTAT_DATA_UINT64);
338 - kstat_named_init(&ixgbe_ks->qprc[14], "queue_pkts_recvd [14]",
339 - KSTAT_DATA_UINT64);
340 - kstat_named_init(&ixgbe_ks->qprc[15], "queue_pkts_recvd [15]",
341 - KSTAT_DATA_UINT64);
342 -
343 - kstat_named_init(&ixgbe_ks->qptc[0], "queue_pkts_xmitd [ 0]",
344 - KSTAT_DATA_UINT64);
345 - kstat_named_init(&ixgbe_ks->qptc[1], "queue_pkts_xmitd [ 1]",
346 - KSTAT_DATA_UINT64);
347 - kstat_named_init(&ixgbe_ks->qptc[2], "queue_pkts_xmitd [ 2]",
348 - KSTAT_DATA_UINT64);
349 - kstat_named_init(&ixgbe_ks->qptc[3], "queue_pkts_xmitd [ 3]",
350 - KSTAT_DATA_UINT64);
351 - kstat_named_init(&ixgbe_ks->qptc[4], "queue_pkts_xmitd [ 4]",
352 - KSTAT_DATA_UINT64);
353 - kstat_named_init(&ixgbe_ks->qptc[5], "queue_pkts_xmitd [ 5]",
354 - KSTAT_DATA_UINT64);
355 - kstat_named_init(&ixgbe_ks->qptc[6], "queue_pkts_xmitd [ 6]",
356 - KSTAT_DATA_UINT64);
357 - kstat_named_init(&ixgbe_ks->qptc[7], "queue_pkts_xmitd [ 7]",
358 - KSTAT_DATA_UINT64);
359 - kstat_named_init(&ixgbe_ks->qptc[8], "queue_pkts_xmitd [ 8]",
360 - KSTAT_DATA_UINT64);
361 - kstat_named_init(&ixgbe_ks->qptc[9], "queue_pkts_xmitd [ 9]",
362 - KSTAT_DATA_UINT64);
363 - kstat_named_init(&ixgbe_ks->qptc[10], "queue_pkts_xmitd [10]",
364 - KSTAT_DATA_UINT64);
365 - kstat_named_init(&ixgbe_ks->qptc[11], "queue_pkts_xmitd [11]",
366 - KSTAT_DATA_UINT64);
367 - kstat_named_init(&ixgbe_ks->qptc[12], "queue_pkts_xmitd [12]",
368 - KSTAT_DATA_UINT64);
369 - kstat_named_init(&ixgbe_ks->qptc[13], "queue_pkts_xmitd [13]",
370 - KSTAT_DATA_UINT64);
371 - kstat_named_init(&ixgbe_ks->qptc[14], "queue_pkts_xmitd [14]",
372 - KSTAT_DATA_UINT64);
373 - kstat_named_init(&ixgbe_ks->qptc[15], "queue_pkts_xmitd [15]",
374 - KSTAT_DATA_UINT64);
375 -
376 - kstat_named_init(&ixgbe_ks->qbrc[0], "queue_bytes_recvd [ 0]",
377 - KSTAT_DATA_UINT64);
378 - kstat_named_init(&ixgbe_ks->qbrc[1], "queue_bytes_recvd [ 1]",
379 - KSTAT_DATA_UINT64);
380 - kstat_named_init(&ixgbe_ks->qbrc[2], "queue_bytes_recvd [ 2]",
381 - KSTAT_DATA_UINT64);
382 - kstat_named_init(&ixgbe_ks->qbrc[3], "queue_bytes_recvd [ 3]",
383 - KSTAT_DATA_UINT64);
384 - kstat_named_init(&ixgbe_ks->qbrc[4], "queue_bytes_recvd [ 4]",
385 - KSTAT_DATA_UINT64);
386 - kstat_named_init(&ixgbe_ks->qbrc[5], "queue_bytes_recvd [ 5]",
387 - KSTAT_DATA_UINT64);
388 - kstat_named_init(&ixgbe_ks->qbrc[6], "queue_bytes_recvd [ 6]",
389 - KSTAT_DATA_UINT64);
390 - kstat_named_init(&ixgbe_ks->qbrc[7], "queue_bytes_recvd [ 7]",
391 - KSTAT_DATA_UINT64);
392 - kstat_named_init(&ixgbe_ks->qbrc[8], "queue_bytes_recvd [ 8]",
393 - KSTAT_DATA_UINT64);
394 - kstat_named_init(&ixgbe_ks->qbrc[9], "queue_bytes_recvd [ 9]",
395 - KSTAT_DATA_UINT64);
396 - kstat_named_init(&ixgbe_ks->qbrc[10], "queue_bytes_recvd [10]",
397 - KSTAT_DATA_UINT64);
398 - kstat_named_init(&ixgbe_ks->qbrc[11], "queue_bytes_recvd [11]",
399 - KSTAT_DATA_UINT64);
400 - kstat_named_init(&ixgbe_ks->qbrc[12], "queue_bytes_recvd [12]",
401 - KSTAT_DATA_UINT64);
402 - kstat_named_init(&ixgbe_ks->qbrc[13], "queue_bytes_recvd [13]",
403 - KSTAT_DATA_UINT64);
404 - kstat_named_init(&ixgbe_ks->qbrc[14], "queue_bytes_recvd [14]",
405 - KSTAT_DATA_UINT64);
406 - kstat_named_init(&ixgbe_ks->qbrc[15], "queue_bytes_recvd [15]",
407 - KSTAT_DATA_UINT64);
408 -
409 - kstat_named_init(&ixgbe_ks->qbtc[0], "queue_bytes_xmitd [ 0]",
410 - KSTAT_DATA_UINT64);
411 - kstat_named_init(&ixgbe_ks->qbtc[1], "queue_bytes_xmitd [ 1]",
412 - KSTAT_DATA_UINT64);
413 - kstat_named_init(&ixgbe_ks->qbtc[2], "queue_bytes_xmitd [ 2]",
414 - KSTAT_DATA_UINT64);
415 - kstat_named_init(&ixgbe_ks->qbtc[3], "queue_bytes_xmitd [ 3]",
416 - KSTAT_DATA_UINT64);
417 - kstat_named_init(&ixgbe_ks->qbtc[4], "queue_bytes_xmitd [ 4]",
418 - KSTAT_DATA_UINT64);
419 - kstat_named_init(&ixgbe_ks->qbtc[5], "queue_bytes_xmitd [ 5]",
420 - KSTAT_DATA_UINT64);
421 - kstat_named_init(&ixgbe_ks->qbtc[6], "queue_bytes_xmitd [ 6]",
422 - KSTAT_DATA_UINT64);
423 - kstat_named_init(&ixgbe_ks->qbtc[7], "queue_bytes_xmitd [ 7]",
424 - KSTAT_DATA_UINT64);
425 - kstat_named_init(&ixgbe_ks->qbtc[8], "queue_bytes_xmitd [ 8]",
426 - KSTAT_DATA_UINT64);
427 - kstat_named_init(&ixgbe_ks->qbtc[9], "queue_bytes_xmitd [ 9]",
428 - KSTAT_DATA_UINT64);
429 - kstat_named_init(&ixgbe_ks->qbtc[10], "queue_bytes_xmitd [10]",
430 - KSTAT_DATA_UINT64);
431 - kstat_named_init(&ixgbe_ks->qbtc[11], "queue_bytes_xmitd [11]",
432 - KSTAT_DATA_UINT64);
433 - kstat_named_init(&ixgbe_ks->qbtc[12], "queue_bytes_xmitd [12]",
434 - KSTAT_DATA_UINT64);
435 - kstat_named_init(&ixgbe_ks->qbtc[13], "queue_bytes_xmitd [13]",
436 - KSTAT_DATA_UINT64);
437 - kstat_named_init(&ixgbe_ks->qbtc[14], "queue_bytes_xmitd [14]",
438 - KSTAT_DATA_UINT64);
439 - kstat_named_init(&ixgbe_ks->qbtc[15], "queue_bytes_xmitd [15]",
440 - KSTAT_DATA_UINT64);
441 -
442 408 kstat_named_init(&ixgbe_ks->mspdc, "mac_short_packet_discard",
443 409 KSTAT_DATA_UINT64);
444 410 kstat_named_init(&ixgbe_ks->mpc, "missed_packets",
445 411 KSTAT_DATA_UINT64);
446 412 kstat_named_init(&ixgbe_ks->mlfc, "mac_local_fault",
447 413 KSTAT_DATA_UINT64);
448 414 kstat_named_init(&ixgbe_ks->mrfc, "mac_remote_fault",
449 415 KSTAT_DATA_UINT64);
450 416 kstat_named_init(&ixgbe_ks->rlec, "recv_length_err",
451 417 KSTAT_DATA_UINT64);
452 418 kstat_named_init(&ixgbe_ks->lxontxc, "link_xon_xmitd",
453 419 KSTAT_DATA_UINT64);
454 420 kstat_named_init(&ixgbe_ks->lxonrxc, "link_xon_recvd",
455 421 KSTAT_DATA_UINT64);
456 422 kstat_named_init(&ixgbe_ks->lxofftxc, "link_xoff_xmitd",
457 423 KSTAT_DATA_UINT64);
458 424 kstat_named_init(&ixgbe_ks->lxoffrxc, "link_xoff_recvd",
459 425 KSTAT_DATA_UINT64);
460 426 kstat_named_init(&ixgbe_ks->ruc, "recv_undersize",
461 427 KSTAT_DATA_UINT64);
462 428 kstat_named_init(&ixgbe_ks->rfc, "recv_fragment",
463 429 KSTAT_DATA_UINT64);
464 430 kstat_named_init(&ixgbe_ks->roc, "recv_oversize",
465 431 KSTAT_DATA_UINT64);
466 432 kstat_named_init(&ixgbe_ks->rjc, "recv_jabber",
467 433 KSTAT_DATA_UINT64);
468 434 kstat_named_init(&ixgbe_ks->rnbc, "recv_no_buffer",
469 435 KSTAT_DATA_UINT64);
470 436 kstat_named_init(&ixgbe_ks->lroc, "lro_pkt_count",
471 437 KSTAT_DATA_UINT64);
472 438
473 439 kstat_named_init(&ixgbe_ks->dev_gone, "device_gone",
474 440 KSTAT_DATA_UINT64);
475 441 /*
476 442 * Function to provide kernel stat update on demand
477 443 */
478 444 ks->ks_update = ixgbe_update_stats;
479 445
480 446 ks->ks_private = (void *)ixgbe;
481 447
482 448 /*
483 449 * Add kstat to systems kstat chain
484 450 */
485 451 kstat_install(ks);
486 452
487 453 return (IXGBE_SUCCESS);
488 454 }
489 455
490 456 /*
491 457 * Retrieve a value for one of the statistics.
492 458 */
493 459 int
494 460 ixgbe_m_stat(void *arg, uint_t stat, uint64_t *val)
495 461 {
496 462 ixgbe_t *ixgbe = (ixgbe_t *)arg;
497 463 struct ixgbe_hw *hw = &ixgbe->hw;
498 464 ixgbe_stat_t *ixgbe_ks;
499 465 int i;
500 466 ixgbe_link_speed speeds = 0;
501 467
502 468 ixgbe_ks = (ixgbe_stat_t *)ixgbe->ixgbe_ks->ks_data;
503 469
504 470 mutex_enter(&ixgbe->gen_lock);
505 471
506 472 /*
507 473 * We cannot always rely on the common code maintaining
508 474 * hw->phy.speeds_supported, therefore we fall back to use the recorded
509 475 * supported speeds which were obtained during instance init in
510 476 * ixgbe_init_params().
511 477 */
512 478 speeds = hw->phy.speeds_supported;
513 479 if (speeds == 0)
514 480 speeds = ixgbe->speeds_supported;
515 481
516 482 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
517 483 mutex_exit(&ixgbe->gen_lock);
518 484 return (ECANCELED);
519 485 }
520 486
521 487 switch (stat) {
522 488 case MAC_STAT_IFSPEED:
523 489 *val = ixgbe->link_speed * 1000000ull;
524 490 break;
525 491
526 492 case MAC_STAT_MULTIRCV:
527 493 ixgbe_ks->mprc.value.ui64 +=
528 494 IXGBE_READ_REG(hw, IXGBE_MPRC);
529 495 *val = ixgbe_ks->mprc.value.ui64;
530 496 break;
531 497
532 498 case MAC_STAT_BRDCSTRCV:
533 499 ixgbe_ks->bprc.value.ui64 +=
534 500 IXGBE_READ_REG(hw, IXGBE_BPRC);
535 501 *val = ixgbe_ks->bprc.value.ui64;
536 502 break;
537 503
538 504 case MAC_STAT_MULTIXMT:
539 505 ixgbe_ks->mptc.value.ui64 +=
540 506 IXGBE_READ_REG(hw, IXGBE_MPTC);
↓ open down ↓ |
89 lines elided |
↑ open up ↑ |
541 507 *val = ixgbe_ks->mptc.value.ui64;
542 508 break;
543 509
544 510 case MAC_STAT_BRDCSTXMT:
545 511 ixgbe_ks->bptc.value.ui64 +=
546 512 IXGBE_READ_REG(hw, IXGBE_BPTC);
547 513 *val = ixgbe_ks->bptc.value.ui64;
548 514 break;
549 515
550 516 case MAC_STAT_NORCVBUF:
551 - for (i = 0; i < 8; i++) {
517 + /*
518 + * The QPRDC[0] register maps to the same kstat as the
519 + * old RNBC register because they have equivalent
520 + * semantics.
521 + */
522 + if (hw->mac.type == ixgbe_mac_82598EB) {
523 + for (i = 0; i < 8; i++) {
524 + ixgbe_ks->rnbc.value.ui64 +=
525 + IXGBE_READ_REG(hw, IXGBE_RNBC(i));
526 + }
527 + } else {
552 528 ixgbe_ks->rnbc.value.ui64 +=
553 - IXGBE_READ_REG(hw, IXGBE_RNBC(i));
529 + IXGBE_READ_REG(hw, IXGBE_QPRDC(0));
554 530 }
531 +
555 532 *val = ixgbe_ks->rnbc.value.ui64;
556 533 break;
557 534
558 535 case MAC_STAT_IERRORS:
559 536 ixgbe_ks->crcerrs.value.ui64 +=
560 537 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
561 538 ixgbe_ks->illerrc.value.ui64 +=
562 539 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
563 540 ixgbe_ks->errbc.value.ui64 +=
564 541 IXGBE_READ_REG(hw, IXGBE_ERRBC);
565 542 ixgbe_ks->rlec.value.ui64 +=
566 543 IXGBE_READ_REG(hw, IXGBE_RLEC);
567 544 *val = ixgbe_ks->crcerrs.value.ui64 +
568 545 ixgbe_ks->illerrc.value.ui64 +
569 546 ixgbe_ks->errbc.value.ui64 +
570 547 ixgbe_ks->rlec.value.ui64;
571 548 break;
572 549
573 550 case MAC_STAT_RBYTES:
574 - ixgbe_ks->tor.value.ui64 = 0;
575 - for (i = 0; i < 16; i++) {
576 - ixgbe_ks->qbrc[i].value.ui64 +=
577 - IXGBE_READ_REG(hw, IXGBE_QBRC(i));
578 - ixgbe_ks->tor.value.ui64 +=
579 - ixgbe_ks->qbrc[i].value.ui64;
580 - }
551 + ixgbe_ks->tor.value.ui64 += ixgbe_read_tor_value(hw);
581 552 *val = ixgbe_ks->tor.value.ui64;
582 553 break;
583 554
584 555 case MAC_STAT_OBYTES:
585 - ixgbe_ks->tot.value.ui64 = 0;
586 - for (i = 0; i < 16; i++) {
587 - switch (hw->mac.type) {
588 - case ixgbe_mac_82598EB:
589 - ixgbe_ks->qbtc[i].value.ui64 +=
590 - IXGBE_READ_REG(hw, IXGBE_QBTC(i));
591 - break;
592 -
593 - case ixgbe_mac_82599EB:
594 - case ixgbe_mac_X540:
595 - case ixgbe_mac_X550:
596 - case ixgbe_mac_X550EM_x:
597 - case ixgbe_mac_X550EM_a:
598 - ixgbe_ks->qbtc[i].value.ui64 +=
599 - IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
600 - ixgbe_ks->qbtc[i].value.ui64 +=
601 - ((uint64_t)((IXGBE_READ_REG(hw,
602 - IXGBE_QBTC_H(i))) & 0xF) << 32);
603 - break;
604 -
605 - default:
606 - break;
607 - }
608 - ixgbe_ks->tot.value.ui64 +=
609 - ixgbe_ks->qbtc[i].value.ui64;
610 - }
556 + /*
557 + * The controller does not provide a Total Octets
558 + * Transmitted statistic. The closest thing we have is
559 + * Good Octets Transmitted. This makes sense, as what
560 + * does it mean to transmit a packet if it didn't
561 + * actually transmit.
562 + */
563 + ixgbe_ks->got.value.ui64 += ixgbe_read_got_value(hw);
564 + ixgbe_ks->tot.value.ui64 = ixgbe_ks->got.value.ui64;
611 565 *val = ixgbe_ks->tot.value.ui64;
612 566 break;
613 567
614 568 case MAC_STAT_IPACKETS:
615 569 ixgbe_ks->tpr.value.ui64 +=
616 570 IXGBE_READ_REG(hw, IXGBE_TPR);
617 571 *val = ixgbe_ks->tpr.value.ui64;
618 572 break;
619 573
620 574 case MAC_STAT_OPACKETS:
621 575 ixgbe_ks->tpt.value.ui64 +=
622 576 IXGBE_READ_REG(hw, IXGBE_TPT);
623 577 *val = ixgbe_ks->tpt.value.ui64;
624 578 break;
625 579
626 580 /* RFC 1643 stats */
627 581 case ETHER_STAT_FCS_ERRORS:
628 582 ixgbe_ks->crcerrs.value.ui64 +=
629 583 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
630 584 *val = ixgbe_ks->crcerrs.value.ui64;
631 585 break;
632 586
633 587 case ETHER_STAT_TOOLONG_ERRORS:
634 588 ixgbe_ks->roc.value.ui64 +=
635 589 IXGBE_READ_REG(hw, IXGBE_ROC);
636 590 *val = ixgbe_ks->roc.value.ui64;
637 591 break;
638 592
639 593 case ETHER_STAT_MACRCV_ERRORS:
640 594 ixgbe_ks->crcerrs.value.ui64 +=
641 595 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
642 596 ixgbe_ks->illerrc.value.ui64 +=
643 597 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
644 598 ixgbe_ks->errbc.value.ui64 +=
645 599 IXGBE_READ_REG(hw, IXGBE_ERRBC);
646 600 ixgbe_ks->rlec.value.ui64 +=
647 601 IXGBE_READ_REG(hw, IXGBE_RLEC);
648 602 *val = ixgbe_ks->crcerrs.value.ui64 +
649 603 ixgbe_ks->illerrc.value.ui64 +
650 604 ixgbe_ks->errbc.value.ui64 +
651 605 ixgbe_ks->rlec.value.ui64;
652 606 break;
653 607
654 608 /* MII/GMII stats */
655 609 case ETHER_STAT_XCVR_ADDR:
656 610 /* The Internal PHY's MDI address for each MAC is 1 */
657 611 *val = 1;
658 612 break;
659 613
660 614 case ETHER_STAT_XCVR_ID:
661 615 *val = hw->phy.id;
662 616 break;
663 617
664 618 case ETHER_STAT_XCVR_INUSE:
665 619 switch (ixgbe->link_speed) {
666 620 case IXGBE_LINK_SPEED_1GB_FULL:
667 621 *val =
668 622 (hw->phy.media_type == ixgbe_media_type_copper) ?
669 623 XCVR_1000T : XCVR_1000X;
670 624 break;
671 625 case IXGBE_LINK_SPEED_100_FULL:
672 626 *val = (hw->phy.media_type == ixgbe_media_type_copper) ?
673 627 XCVR_100T2 : XCVR_100X;
674 628 break;
675 629 default:
676 630 *val = XCVR_NONE;
677 631 break;
678 632 }
679 633 break;
680 634
681 635 case ETHER_STAT_CAP_10GFDX:
682 636 *val = (speeds & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
683 637 break;
684 638
685 639 case ETHER_STAT_CAP_5000FDX:
686 640 *val = (speeds & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
687 641 break;
688 642
689 643 case ETHER_STAT_CAP_2500FDX:
690 644 *val = (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
691 645 break;
692 646
693 647 case ETHER_STAT_CAP_1000FDX:
694 648 *val = (speeds & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
695 649 break;
696 650
697 651 case ETHER_STAT_CAP_100FDX:
698 652 *val = (speeds & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
699 653 break;
700 654
701 655 case ETHER_STAT_CAP_ASMPAUSE:
702 656 *val = ixgbe->param_asym_pause_cap;
703 657 break;
704 658
705 659 case ETHER_STAT_CAP_PAUSE:
706 660 *val = ixgbe->param_pause_cap;
707 661 break;
708 662
709 663 case ETHER_STAT_CAP_AUTONEG:
710 664 *val = 1;
711 665 break;
712 666
713 667 case ETHER_STAT_ADV_CAP_10GFDX:
714 668 *val = ixgbe->param_adv_10000fdx_cap;
715 669 break;
716 670
717 671 case ETHER_STAT_ADV_CAP_5000FDX:
718 672 *val = ixgbe->param_adv_5000fdx_cap;
719 673 break;
720 674
721 675 case ETHER_STAT_ADV_CAP_2500FDX:
722 676 *val = ixgbe->param_adv_2500fdx_cap;
723 677 break;
724 678
725 679 case ETHER_STAT_ADV_CAP_1000FDX:
726 680 *val = ixgbe->param_adv_1000fdx_cap;
727 681 break;
728 682
729 683 case ETHER_STAT_ADV_CAP_100FDX:
730 684 *val = ixgbe->param_adv_100fdx_cap;
731 685 break;
732 686
733 687 case ETHER_STAT_ADV_CAP_ASMPAUSE:
734 688 *val = ixgbe->param_adv_asym_pause_cap;
735 689 break;
736 690
737 691 case ETHER_STAT_ADV_CAP_PAUSE:
738 692 *val = ixgbe->param_adv_pause_cap;
739 693 break;
740 694
741 695 case ETHER_STAT_ADV_CAP_AUTONEG:
742 696 *val = ixgbe->param_adv_autoneg_cap;
743 697 break;
744 698
745 699 case ETHER_STAT_LP_CAP_10GFDX:
746 700 *val = ixgbe->param_lp_10000fdx_cap;
747 701 break;
748 702
749 703 case ETHER_STAT_LP_CAP_5000FDX:
750 704 *val = ixgbe->param_lp_5000fdx_cap;
751 705 break;
752 706
753 707 case ETHER_STAT_LP_CAP_2500FDX:
754 708 *val = ixgbe->param_lp_2500fdx_cap;
755 709 break;
756 710
757 711 case ETHER_STAT_LP_CAP_1000FDX:
758 712 *val = ixgbe->param_lp_1000fdx_cap;
759 713 break;
760 714
761 715 case ETHER_STAT_LP_CAP_100FDX:
762 716 *val = ixgbe->param_lp_100fdx_cap;
763 717 break;
764 718
765 719 case ETHER_STAT_LP_CAP_ASMPAUSE:
766 720 *val = ixgbe->param_lp_asym_pause_cap;
767 721 break;
768 722
769 723 case ETHER_STAT_LP_CAP_PAUSE:
770 724 *val = ixgbe->param_lp_pause_cap;
771 725 break;
772 726
773 727 case ETHER_STAT_LP_CAP_AUTONEG:
774 728 *val = ixgbe->param_lp_autoneg_cap;
775 729 break;
776 730
777 731 case ETHER_STAT_LINK_ASMPAUSE:
778 732 *val = ixgbe->param_asym_pause_cap;
779 733 break;
780 734
781 735 case ETHER_STAT_LINK_PAUSE:
782 736 *val = ixgbe->param_pause_cap;
783 737 break;
784 738
785 739 case ETHER_STAT_LINK_AUTONEG:
786 740 *val = ixgbe->param_adv_autoneg_cap;
787 741 break;
788 742
789 743 case ETHER_STAT_LINK_DUPLEX:
790 744 *val = ixgbe->link_duplex;
791 745 break;
792 746
793 747 case ETHER_STAT_TOOSHORT_ERRORS:
794 748 ixgbe_ks->ruc.value.ui64 +=
795 749 IXGBE_READ_REG(hw, IXGBE_RUC);
796 750 *val = ixgbe_ks->ruc.value.ui64;
797 751 break;
798 752
799 753 case ETHER_STAT_CAP_REMFAULT:
800 754 *val = ixgbe->param_rem_fault;
801 755 break;
802 756
803 757 case ETHER_STAT_ADV_REMFAULT:
804 758 *val = ixgbe->param_adv_rem_fault;
805 759 break;
806 760
807 761 case ETHER_STAT_LP_REMFAULT:
808 762 *val = ixgbe->param_lp_rem_fault;
809 763 break;
810 764
811 765 case ETHER_STAT_JABBER_ERRORS:
812 766 ixgbe_ks->rjc.value.ui64 +=
813 767 IXGBE_READ_REG(hw, IXGBE_RJC);
814 768 *val = ixgbe_ks->rjc.value.ui64;
815 769 break;
816 770
817 771 default:
818 772 mutex_exit(&ixgbe->gen_lock);
819 773 return (ENOTSUP);
820 774 }
821 775
822 776 mutex_exit(&ixgbe->gen_lock);
823 777
824 778 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
825 779 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
826 780 return (EIO);
827 781 }
828 782
829 783 return (0);
830 784 }
831 785
832 786 /*
833 787 * Retrieve a value for one of the statistics for a particular rx ring
834 788 */
835 789 int
836 790 ixgbe_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
837 791 {
838 792 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)rh;
839 793 ixgbe_t *ixgbe = rx_ring->ixgbe;
840 794
841 795 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
842 796 return (ECANCELED);
843 797 }
844 798
845 799 switch (stat) {
846 800 case MAC_STAT_RBYTES:
847 801 *val = rx_ring->stat_rbytes;
848 802 break;
849 803
850 804 case MAC_STAT_IPACKETS:
851 805 *val = rx_ring->stat_ipackets;
852 806 break;
853 807
854 808 default:
855 809 *val = 0;
856 810 return (ENOTSUP);
857 811 }
858 812
859 813 return (0);
860 814 }
861 815
862 816 /*
863 817 * Retrieve a value for one of the statistics for a particular tx ring
864 818 */
865 819 int
866 820 ixgbe_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
867 821 {
868 822 ixgbe_tx_ring_t *tx_ring = (ixgbe_tx_ring_t *)rh;
869 823 ixgbe_t *ixgbe = tx_ring->ixgbe;
870 824
871 825 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
872 826 return (ECANCELED);
873 827 }
874 828
875 829 switch (stat) {
876 830 case MAC_STAT_OBYTES:
877 831 *val = tx_ring->stat_obytes;
878 832 break;
879 833
880 834 case MAC_STAT_OPACKETS:
881 835 *val = tx_ring->stat_opackets;
882 836 break;
883 837
884 838 default:
885 839 *val = 0;
886 840 return (ENOTSUP);
887 841 }
888 842
889 843 return (0);
890 844 }
↓ open down ↓ |
270 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX